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    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM
    2.
    发明公开
    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240257850A1

    公开(公告)日：2024-08-01

    申请号：US18426825

    申请日：2024-01-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/225 ,  G11C7/1096 ,  G11C7/222

    Abstract: Provided is a memory system including a memory device including a plurality of non-volatile memories, each of the plurality of non-volatile memories being electrically connected to a buffer chip, and a memory controller electrically connected to the buffer chip and configured to transmit a reference clock signal used in correction of a data signal, wherein the buffer chip includes a delay clock generation chain configured to generate a first delay clock signal or a second delay clock signal from the reference clock signal, a first register configured to store the first delay clock signal, and a second register configured to store the second delay clock signal, and wherein the buffer chip is configured to perform compensation on a strobe signal of the data signal based on the first delay clock signal, and perform compensation on the data signal based on the second delay clock signal.

    Impedance calibration circuit and memory device including the same
    4.
    发明授权
    Impedance calibration circuit and memory device including the same 有权

    公开(公告)号：US11115021B2

    公开(公告)日：2021-09-07

    申请号：US17021728

    申请日：2020-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Youngmin Jo ,  Jungjune Park ,  Jindo Byun ,  Dongho Shin ,  Jeongdon Ihm

    IPC: H03K19/00 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/10 ,  H03K19/08

    Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM
    6.
    发明公开
    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240282378A1

    公开(公告)日：2024-08-22

    申请号：US18444848

    申请日：2024-02-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

    IPC: G11C16/08 ,  G11C16/04

    CPC classification number: G11C16/08 ,  G11C16/0483

    Abstract: A memory system includes a memory device having a plurality of non-volatile memories, a buffer chip connected with each of the plurality of non-volatile memories, and a memory controller connected with the buffer chip and configured to provide a data strobe signal and a data signal to the buffer chip. The buffer chip includes a first loop coupled to a sampler circuit and configured to perform first monitoring on the data strobe signal and first duty correction on the data strobe signal based on the first monitoring, and a second loop coupled to a multiplexer and configured to, responsive to the first duty correction, perform second monitoring on the data strobe signal and second duty correction on the data strobe signal based on the second monitoring. The buffer chip is configured to store first and second duty correction information for at least one of the plurality of non-volatile memories.

    SEMICONDUCTOR DEVICE
    8.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240347080A1

    公开(公告)日：2024-10-17

    申请号：US18406726

    申请日：2024-01-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsuk Kang ,  Jeongsu Lee ,  Eunji An ,  Jungjune Park ,  Chiweon Yoon

    IPC: G11C5/14

    CPC classification number: G11C5/147

    Abstract: A semiconductor device includes a first pull-up circuit connected between a first power node supplying a first power voltage and an output node through which a signal is output, and including a plurality of NMOS transistors; a second pull-up circuit connected in parallel to the first pull-up circuit between the first power node and the output node and including a plurality of PMOS transistors; and a control circuit outputting a first pull-up code to the first pull-up circuit and outputting the second pull-up code to the second pull-up circuit. In a first operating mode, the signal swings between a first low level lower than the first power voltage, and a first high level lower than ½ times the first power voltage, resistance of the first pull-up circuit is determined based on the first pull-up code, and resistance of the second pull-up circuit is determined based on the second pull-up code.

    STORAGE DEVICE INCLUDING BUFFER CHIP AND METHOD FOR PER-PIN TRAINING USING BUFFER CHIP
    9.
    发明公开
    STORAGE DEVICE INCLUDING BUFFER CHIP AND METHOD FOR PER-PIN TRAINING USING BUFFER CHIP 审中-公开

    公开(公告)号：US20240321330A1

    公开(公告)日：2024-09-26

    申请号：US18611213

    申请日：2024-03-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Anil KAVALA ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

    IPC: G11C7/22 ,  G11C7/14 ,  H03L7/099

    CPC classification number: G11C7/222 ,  G11C7/14 ,  H03L7/0998

    Abstract: A storage device includes a buffer chip and a memory device. The memory device transmits a random data signal and a data strobe signal to the buffer chip based on a clock signal received from the buffer chip. The buffer chip includes a delay circuit that delays the data strobe signal by a delay time to generate a delayed data strobe signal, a sampler that receives the delayed data strobe signal from the delay circuit and samples the random data signal based on the delayed data strobe signal to generate sampled data, a comparator that compares internal data with the sampled data to generate a comparison result, and a counter module that receives the comparison result from the comparator and determines a target delay based on the comparison result. The buffer chip delays the delayed data strobe signal based on the target delay.

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