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公开(公告)号：US20220115046A1
公开(公告)日：2022-04-14
申请号：US17346853
申请日：2021-06-14
Applicant: SAMSUNG ELECTRONICS CO.,LTD.
Inventor： Hyunsuk Kang , Jungjune Park , Kyoungtae Kang , Junha Lee , Byunghoon Jeong
Abstract: A high resolution impedance adjustment (ZQ) calibration method using a hidden least significant bit (HLSB) is provided. The high resolution ZQ calibration method generates a data input/output (DQ) code of n+1 bits without a calibration time increase by adding the hidden least significant bit (HLSB) to a ZQ code of n bits output in a ZQ calibration operation of an impedance adjustment (ZQ) pad. A change in a termination resistance of the DQ pad is reduced as small as possible by the DQ code of n+1 bits.
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公开(公告)号：US11336266B2
公开(公告)日：2022-05-17
申请号：US17222033
申请日：2021-04-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongho Shin , Kyungtae Kang , Junha Lee , Tongsung Kim , Jangwoo Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.
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公开(公告)号：US12073917B2
公开(公告)日：2024-08-27
申请号：US17404510
申请日：2021-08-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tongsung Kim , Youngmin Jo , Manjae Yang , Chiweon Yoon , Junha Lee , Byunghoon Jeong
CPC classification number: G11C7/222 , G06F1/04 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C29/023 , G11C29/028 , G11C5/145
Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.
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公开(公告)号：US10998888B2
公开(公告)日：2021-05-04
申请号：US16861903
申请日：2020-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongho Shin , Kyungtae Kang , Junha Lee , Tongsung Kim , Jangwoo Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A parameter monitoring circuit includes a code generation circuit configured to generate a first code, to which a first offset is applied, and a second code, to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by respectively applying the first code and the second code to a current parameter; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error in the current parameter, based on the first comparison result and the second comparison result.
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公开(公告)号：US11581025B2
公开(公告)日：2023-02-14
申请号：US17346853
申请日：2021-06-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunsuk Kang , Jungjune Park , Kyoungtae Kang , Junha Lee , Byunghoon Jeong
Abstract: A high resolution impedance adjustment (ZQ) calibration method using a hidden least significant bit (HLSB) is provided. The high resolution ZQ calibration method generates a data input/output (DQ) code of n+1 bits without a calibration time increase by adding the hidden least significant bit (HLSB) to a ZQ code of n bits output in a ZQ calibration operation of an impedance adjustment (ZQ) pad. A change in a termination resistance of the DQ pad is reduced as small as possible by the DQ code of n+1 bits.
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Patent Agency Ranking
公开(公告)号：US11127462B2
公开(公告)日：2021-09-21
申请号：US16834025
申请日：2020-03-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junha Lee , Seonkyoo Lee , Jeongdon Ihm , Byunghoon Jeong
IPC: G11C16/06 , H01L23/66 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
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公开(公告)号：US20250104749A1
公开(公告)日：2025-03-27
申请号：US18604593
申请日：2024-03-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dongho Shin , Kangyoon Lee , Seonkyoo Lee , Junha Lee
IPC: G11C7/22
Abstract: A method of calibrating impedance of a memory device including a data transmitter includes: outputting a comparison signal by comparing a power supply voltage and a reference voltage, the power supply voltage being supplied to the data transmitter when the data transmitter is driven; storing a voltage level of the reference voltage when the comparison signal changes logical state; adjusting the reference voltage based on the comparison signal such that the voltage level of the reference voltage increases or decreases; and calibrating an output impedance of the memory device based on a digital code corresponding to an average reference voltage level, the average reference voltage level being obtained by averaging a prescribed number of voltage levels of the reference voltage stored as a result of repeatedly outputting the comparison signal, storing the voltage level of the reference voltage, and adjusting the reference voltage.
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公开(公告)号：US11915781B2
公开(公告)日：2024-02-27
申请号：US17938214
申请日：2022-10-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dongho Shin , Jungjune Park , Kyoungtae Kang , Chiweon Yoon , Junha Lee , Byunghoon Jeong
CPC classification number: G11C7/1051 , H03K19/0005 , G11C2207/2254
Abstract: An apparatus and method for ZQ calibration, including determining a strong driver circuit and a weak driver circuit, which are related to an input/output (I/O) circuit connected to a signal pin, at power-up of the I/O circuit; providing a ZQ calibration code related to a sweep code to one from among the strong driver circuit and the weak driver circuit according to ZQ calibration conditions; and providing a ZQ calibration code related to a fixed code to an unselected circuit, thereby adjusting a termination resistance of the signal pin.
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公开(公告)号：US11475955B2
公开(公告)日：2022-10-18
申请号：US17393784
申请日：2021-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junha Lee , Seonkyoo Lee , Jeongdon Ihm , Byunghoon Jeong
IPC: G11C16/06 , H01L23/66 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
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公开(公告)号：US11217283B2
公开(公告)日：2022-01-04
申请号：US17012845
申请日：2020-09-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junha Lee , Seonkyoo Lee , Jeongdon Ihm , Byunghoon Jeong
IPC: G11C7/10 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
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