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    Interface circuit for processing commands, memory device including the same, storage device, and method of operating the memory device
    3.
    发明授权
    Interface circuit for processing commands, memory device including the same, storage device, and method of operating the memory device 有权

    公开(公告)号：US11199975B2

    公开(公告)日：2021-12-14

    申请号：US16861802

    申请日：2020-04-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon Na ,  Jangwoo Lee ,  Jeongdon Ihm

    IPC: G06F13/00 ,  G06F3/06

    Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

    Interface circuit, memory device, storage device, and method of operating the memory device
    5.
    发明授权
    Interface circuit, memory device, storage device, and method of operating the memory device 有权

    公开(公告)号：US11960728B2

    公开(公告)日：2024-04-16

    申请号：US17536506

    申请日：2021-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon Na ,  Jangwoo Lee ,  Jeongdon Ihm

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

    Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

    STORAGE DEVICE GENERATING MULTI-LEVEL CHIP ENABLE SIGNAL AND OPERATING METHOD THEREOF
    8.
    发明申请
    STORAGE DEVICE GENERATING MULTI-LEVEL CHIP ENABLE SIGNAL AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20220236917A1

    公开(公告)日：2022-07-28

    申请号：US17479194

    申请日：2021-09-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsuk Kang ,  Daehoon Na ,  Chiweon Yoon

    IPC: G06F3/06 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: A storage device includes a controller including first and second pins and configured to output a multi-level chip enable signal through the second pin, and a memory device. The memory device includes third and fourth pins respectively connected to the first and second pins, and a plurality of memory chips commonly connected to the fourth pin. The plurality of memory chips respectively include a plurality of resistors connected to one another in a daisy-chain structure between the third pin and a first voltage terminal. The plurality of memory chips are configured to respectively generate a plurality of reference voltage periods that divide between a voltage level of the third pin and a voltage level of the first voltage terminal based on the plurality of resistors.

    Integrated circuit and storage device including integrated circuit
    9.
    发明授权
    Integrated circuit and storage device including integrated circuit 有权

    公开(公告)号：US09897650B2

    公开(公告)日：2018-02-20

    申请号：US14957987

    申请日：2015-12-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon Na ,  ChaeHoon Kim ,  HyunJin Kim ,  Jangwoo Lee ,  Jeongdon Ihm

    IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317

    CPC classification number: G01R31/31716 ,  G01R31/2884 ,  G01R31/3177

    Abstract: An integrated circuit including first pads and second pads, a first receiver circuit and a first driver circuit respectively connected to the first pad, a second receiver circuit and a second driver circuit respectively connected to the second pad, and a first loopback circuit having a first input terminal electrically connected to the first receiver circuit, a first output terminal electrically connected to the first driver circuit, a second output terminal electrically connected to the second driver circuit, and a second input terminal electrically connected to the second receiver circuit may be provided. At a normal mode, the first loopback circuit electrically connects the first input terminal to the second output terminal and electrically connects the second input terminal to the first output terminal. At a test mode, the first loopback circuit electrically connects the first input terminal to the first output terminal.

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