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    MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE
    5.
    发明公开
    MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE 审中-公开

    公开(公告)号：US20230179193A1

    公开(公告)日：2023-06-08

    申请号：US17866517

    申请日：2022-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon ,  Byungkwan Chun ,  Byunghoon Jeong

    IPC: H03K5/14 ,  H03K5/135 ,  H03L7/081

    CPC classification number: H03K5/14 ,  H03K5/135 ,  H03L7/0816 ,  H03K2005/00247

    Abstract: A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

    Nonvolatile memory device supporting high-efficiency I/O interface
    6.
    发明授权
    Nonvolatile memory device supporting high-efficiency I/O interface 有权

    公开(公告)号：US11372593B2

    公开(公告)日：2022-06-28

    申请号：US17168620

    申请日：2021-02-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seonkyoo Lee ,  Jeongdon Ihm ,  Chiweon Yoon ,  Byunghoon Jeong

    IPC: G06F3/06 ,  G11C16/26 ,  G06F1/06 ,  G11C16/04 ,  G11C16/10 ,  G06F13/16

    Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

    IMPEDANCE CALIBRATION CIRCUIT AND METHOD OF CALIBRATING IMPEDANCE IN MEMORY DEVICE
    7.
    发明申请
    IMPEDANCE CALIBRATION CIRCUIT AND METHOD OF CALIBRATING IMPEDANCE IN MEMORY DEVICE 有权

    公开(公告)号：US20220148630A1

    公开(公告)日：2022-05-12

    申请号：US17352527

    申请日：2021-06-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

    IPC: G11C7/10 ,  H03K19/00

    Abstract: An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.

    MEMORY DEVICE SUPPORTING DBI INTERFACE AND OPERATING METHOD OF MEMORY DEVICE
    9.
    发明申请
    MEMORY DEVICE SUPPORTING DBI INTERFACE AND OPERATING METHOD OF MEMORY DEVICE 有权

    公开(公告)号：US20220101895A1

    公开(公告)日：2022-03-31

    申请号：US17477931

    申请日：2021-09-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNGMIN JO ,  Byunghoon Jeong ,  TONGSUNG KIM ,  CHIWEON YOON ,  SEONKYOO LEE

    IPC: G11C7/10

    Abstract: A memory device includes a memory cell array, a page buffer, a control logic circuit, a plurality of input/output pins, a data bus inversion (DBI) pin, and an interface circuit. The page buffer is connected to the memory cell array. The control logic circuit is configured to control an operation of the memory cell array. The plurality of input/output pins receive a plurality of data signals from the controller. The DBI pin receives a DBI signal from the controller. The interface circuit count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the data signals and the DBI signal and provide the data signals to the page buffer or the control logic circuit based on the first number and the second number.

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