公开(公告)号：US20220208696A1

公开(公告)日：2022-06-30

申请号：US17378831

申请日：2021-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEGOO LEE

IPC: H01L23/00 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11573

Abstract: A vertical memory device includes a cell stacked structure on a substrate, a support structure and cell contact plugs. The cell stacked structure includes gate patterns spaced apart from each other in a vertical direction and insulation layers between the gate patterns. The gate patterns extend in a first direction, and edges of the gate patterns along the first direction include step portions having step shape. The support structure passes through the cell stacked structure and the step portion of one of the gate patterns, and includes a spacer layer having cup shape, first metal patterns having ring shape, and a second metal pattern filling an inner space of the spacer layer. The cell contact plugs are on the step portions. The first metal patterns are at the same vertical levels of the gate patterns. Sidewalls of the first metal patterns are adjacent to sidewalls of the gate patterns.

公开(公告)号：US20160240555A1

公开(公告)日：2016-08-18

申请号：US15141263

申请日：2016-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEGOO LEE ,  YOUNGWOO PARK

IPC: H01L27/115 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3D semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns.

公开(公告)号：US20150357346A1

公开(公告)日：2015-12-10

申请号：US14831449

申请日：2015-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYONG-HYUN JANG ,  JUHYUNG KIM ,  WOON KYUNG LEE ,  JAEGOO LEE ,  CHAEHO KIM ,  JUNKYU YANG ,  PHIL OUK NAM ,  JAEYOUNG AHN ,  KlHYUN HWANG

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/10 ,  H01L23/528 ,  H01L29/423 ,  H01L29/04

CPC classification number: H01L29/792 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Abstract translation: 一种半导体存储器件及其制造方法。 该器件包括垂直堆叠在衬底的顶表面上的多个栅极，该衬底的顶表面上形成有在该衬底中形成的外延层，垂直穿过该栅极的垂直沟道以与该外延层电连接;以及存储层，设置在该垂直沟道 和大门。 外延层具有位于最下面一个栅极的底表面和基板的顶表面之间的高度的顶表面。