公开(公告)号：US20180308859A1

公开(公告)日：2018-10-25

申请号：US15849121

申请日：2017-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HOON CHOI ,  SUNGGIL KIM ,  SEULYE KIM ,  HONGSUK KIM ,  PHIL OUK NAM ,  JAEYOUNG AHN

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/06 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/7926

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

公开(公告)号：US20190333937A1

公开(公告)日：2019-10-31

申请号：US16509169

申请日：2019-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HOON CHOI ,  SUNGGIL KIM ,  SEULYE KIM ,  HONGSUK KIM ,  PHIL OUK NAM ,  JAEYOUNG AHN

IPC: H01L27/11582 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11565

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

公开(公告)号：US20210320123A1

公开(公告)日：2021-10-14

申请号：US17036594

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGSOO LEE ,  CHAEHO KIM ,  WOOSUNG LEE ,  PHIL OUK NAM ,  JUNGGEUN JEE

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/535

Abstract: Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.

公开(公告)号：US20150357346A1

公开(公告)日：2015-12-10

申请号：US14831449

申请日：2015-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYONG-HYUN JANG ,  JUHYUNG KIM ,  WOON KYUNG LEE ,  JAEGOO LEE ,  CHAEHO KIM ,  JUNKYU YANG ,  PHIL OUK NAM ,  JAEYOUNG AHN ,  KlHYUN HWANG

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/10 ,  H01L23/528 ,  H01L29/423 ,  H01L29/04

CPC classification number: H01L29/792 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Abstract translation: 一种半导体存储器件及其制造方法。 该器件包括垂直堆叠在衬底的顶表面上的多个栅极，该衬底的顶表面上形成有在该衬底中形成的外延层，垂直穿过该栅极的垂直沟道以与该外延层电连接;以及存储层，设置在该垂直沟道 和大门。 外延层具有位于最下面一个栅极的底表面和基板的顶表面之间的高度的顶表面。