公开(公告)号：US20220122673A1

公开(公告)日：2022-04-21

申请号：US17227501

申请日：2021-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGYEON KIM ,  DAESEOK BYEON ,  PANSUK KWAK ,  HONGSOO JEON

IPC: G11C16/24 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C16/26

Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

公开(公告)号：US20250142829A1

公开(公告)日：2025-05-01

申请号：US18897719

申请日：2024-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGYEON KIM ,  IN HO KANG ,  SUKKANG SUNG ,  BEAKHYUNG CHO

IPC: H10B43/40 ,  G11C5/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L25/065 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B80/00

Abstract: A memory device is provided. The memory device includes: a memory cell array implemented in a first chip; and a peripheral circuit implemented in a second chip and a third chip which overlaps the first chip along a vertical direction. The peripheral circuit includes: a first peripheral circuit implemented in the second chip and the third chip; a second peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a third peripheral circuit implemented in the third chip and including at least one low-voltage transistor. The first peripheral circuit includes: a first sub-peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a second sub-peripheral circuit implemented in the third chip and including at least one low-voltage transistor.

公开(公告)号：US20220406385A1

公开(公告)日：2022-12-22

申请号：US17898885

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGYEON KIM ,  DAESEOK BYEON ,  PANSUK KWAK ,  HONGSOO JEON

IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

公开(公告)号：US20240038603A1

公开(公告)日：2024-02-01

申请号：US18103747

申请日：2023-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunhaeng Heo ,  SUNGHOON KIM ,  JAEICK SON ,  SEUNGYEON KIM

IPC: H01L21/66 ,  H10B80/00

CPC classification number: H01L22/32 ,  H10B80/00

Abstract: A semiconductor chip including a guard ring that surrounds edges of a semiconductor substrate, an internal circuit structure that is formed on the semiconductor substrate and that includes a memory cell array region and a peripheral circuit region, and a crack detection circuit that is located between the guard ring and the internal circuit structure and that detects whether a crack occurs. The semiconductor chip further includes first to fourth chamfer regions having different shapes and sizes depending on the position of a pad or the design arrangement of the internal circuit structure.

公开(公告)号：US20250122061A1

公开(公告)日：2025-04-17

申请号：US18908258

申请日：2024-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： DAEWOONG HAN ,  SEUNGYEON KIM ,  Minsu CHANG ,  JUN-WON JANG ,  TAESIN HA

IPC: B66F11/04 ,  B66C3/00 ,  B66F17/00

Abstract: A platform system includes a station including a moving portion and a guide configured to guide movement of the moving portion, and a manipulator configured to pick up an object from the moving portion or to place the object on the moving portion, where the moving portion is configured to move in response to the manipulator picking up the object from the moving portion or placing the object on the moving portion.

公开(公告)号：US20220301633A1

公开(公告)日：2022-09-22

申请号：US17693013

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MYEONG-WOO LEE ,  SEUNGYEON KIM ,  DONGHA SHIN ,  BEAKHYUNG CHO

IPC: G11C16/16 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30 ,  G11C7/10

Abstract: A nonvolatile memory device includes a plurality of bit lines that is connected with a plurality of cell strings, a common source line that is connected with the plurality of cell strings, at least one dummy bit line that is provided between the common source line and the plurality of bit lines, a control logic circuit that generates at least one dummy bit line driving signal in response to a command from an external device, and a dummy bit line driver that selectively provides a first voltage to the at least one dummy bit line in response to the dummy bit line driving signal.

公开(公告)号：US20200381037A1

公开(公告)日：2020-12-03

申请号：US16840596

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGBUM KIM ,  SUNGHOON KIM ,  SEUNGYEON KIM

IPC: G11C11/408 ,  G11C11/4099 ,  G11C5/02 ,  H01L27/24

Abstract: A memory device including a first memory cell array including first memory cells stacked vertically on a first memory cell array region of a top surface of a substrate; a second memory cell array including second memory cells stacked vertically on a second memory cell array region of the top surface; first word lines coupled to the first memory cells and including a subset of first word lines and remaining first word lines; second word lines coupled to the second memory cells and including a subset of second word lines and remaining second word lines; and a row decoder, including a plurality of merge pass transistors each commonly connected to a respective one of the subset of first word lines and a respective one of the subset of second word lines, disposed in a region of the top surface between the first and second cell array regions.