公开(公告)号：US10548500B2

公开(公告)日：2020-02-04

申请号：US14947640

申请日：2015-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se-hoon Lim ,  Jun-hyung Park ,  Hee-jae Jo ,  Jang-beom Yang ,  Jae-min Jung ,  Eun-mi Oh ,  Jong-ho Choi ,  Jun-ho Koh ,  Chang-Hyun Lee ,  Yong-hyun Lim ,  Hae-in Chun

IPC: A61B5/0478 ,  A61B5/00 ,  A61B5/04

Abstract: An apparatus for measuring bioelectrical signals is provided. The apparatus includes a sensor electrode, a sensor support, and a main body. The sensor electrode has a tapering portion that narrows toward one end and a protruding portion that extends from the one end of the tapering portion, contacts a body part, and senses bioelectrical signals. The sensor support maintains the contact between the sensor electrode and the body part. The main body is connected to the sensor support and is wearable on a living body.

公开(公告)号：US09978674B2

公开(公告)日：2018-05-22

申请号：US15479856

申请日：2017-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-woo Kim ,  Jae-min Jung ,  Ji-yong Park ,  Jeong-kyu Ha ,  Woon-bae Kim

IPC: H01L33/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/29 ,  H01L23/488 ,  H01L33/62

CPC classification number: H01L23/4985 ,  H01L23/29 ,  H01L23/488 ,  H01L23/4922 ,  H01L24/29 ,  H01L24/32 ,  H01L25/167 ,  H01L33/48 ,  H01L33/62 ,  H01L2924/143 ,  H01L2924/186

Abstract: Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF semiconductor package includes a film substrate, a conductive interconnection located on at least one surface of the film substrate and an output pin connected to the conductive interconnection and located at one edge on a first surface of the film substrate, a semiconductor chip connected to the conductive interconnection and mounted on the first surface of the film substrate, a solder resist layer on the first surface of the film substrate to cover at least a portion of the conductive interconnection, and at least one barrier dam on the solder resist layer between the semiconductor chip and the output pin.

公开(公告)号：US10134667B2

公开(公告)日：2018-11-20

申请号：US15964342

申请日：2018-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-woo Kim ,  Jae-min Jung ,  Ji-yong Park ,  Jeong-kyu Ha ,  Woon-bae Kim

IPC: H01L33/48 ,  H01L23/498 ,  H01L23/29 ,  H01L23/00 ,  H01L23/488 ,  H01L33/62 ,  H01L23/492 ,  H01L25/16

Abstract: Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF semiconductor package includes a film substrate, a conductive interconnection located on at least one surface of the film substrate and an output pin connected to the conductive interconnection and located at one edge on a first surface of the film substrate, a semiconductor chip connected to the conductive interconnection and mounted on the first surface of the film substrate, a solder resist layer on the first surface of the film substrate to cover at least a portion of the conductive interconnection, and at least one barrier dam on the solder resist layer between the semiconductor chip and the output pin.

公开(公告)号：US20180247882A1

公开(公告)日：2018-08-30

申请号：US15964342

申请日：2018-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-woo Kim ,  Jae-min Jung ,  Ji-yong Park ,  Jeong-kyu Ha ,  Woon-bae Kim

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/00 ,  H01L33/62 ,  H01L23/488 ,  H01L33/48

CPC classification number: H01L23/4985 ,  H01L23/29 ,  H01L23/488 ,  H01L23/4922 ,  H01L24/29 ,  H01L24/32 ,  H01L25/167 ,  H01L33/48 ,  H01L33/62 ,  H01L2924/143 ,  H01L2924/186

Abstract: Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF semiconductor package includes a film substrate, a conductive interconnection located on at least one surface of the film substrate and an output pin connected to the conductive interconnection and located at one edge on a first surface of the film substrate, a semiconductor chip connected to the conductive interconnection and mounted on the first surface of the film substrate, a solder resist layer on the first surface of the film substrate to cover at least a portion of the conductive interconnection, and at least one barrier dam on the solder resist layer between the semiconductor chip and the output pin.