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    SEMICONDUCTOR PACKAGE INCLUDING A LOWER SUBSTRATE AND AN UPPER SUBSTRATE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING A LOWER SUBSTRATE AND AN UPPER SUBSTRATE 有权

    公开(公告)号：US20230021867A1

    公开(公告)日：2023-01-26

    申请号：US17715417

    申请日：2022-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD

    Inventor： Choongbin YIM ,  Jongbo SHIM ,  Jihwang KIM

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

    Abstract: A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip and including a core layer, an upper wiring layer, a plurality of dummy structures, and a solder resist layer, wherein the core layer has through-holes, wherein the plurality of dummy structures are disposed in the through-holes and are electrically insulated from the upper wiring layer, and wherein the solder resist layer covers the upper wiring layer and extends in the through-holes; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant disposed between the lower substrate and the upper substrate and encapsulating at least a portion of each of the semiconductor chip and the connection structure; and a connection bump disposed on the lower substrate.

    SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230063578A1

    公开(公告)日：2023-03-02

    申请号：US17712489

    申请日：2022-04-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eunho CHO ,  Jihwang KIM ,  Sunchul KIM

    IPC: H01L23/498 ,  H01L23/31

    Abstract: A semiconductor package is provided. The semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate, and electrically connected to the lower wiring layer; an upper substrate disposed on the semiconductor chip, and including an upper wiring layer; a first connection structure disposed on the lower wiring layer, and having a first hollow open toward the upper substrate; a second connection structure disposed below the upper wiring layer, and having a second hollow open toward the lower substrate; a conductive connection member disposed between the first connection structure and the second connection structure, and filling at least a portion of the first hollow; and an encapsulant disposed between the lower substrate and the upper substrate, and encapsulating at least a portion of each of the semiconductor chip, the first connection structure and the second connection structure.

    SEMICONDUCTOR PACKAGE WITH INTERPOSER
    3.
    发明申请
    SEMICONDUCTOR PACKAGE WITH INTERPOSER 有权

    公开(公告)号：US20220302035A1

    公开(公告)日：2022-09-22

    申请号：US17835768

    申请日：2022-06-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Choongbin YIM ,  Jungwoo KIM ,  Jihwang KIM ,  Jongbo SHIM ,  Kyoungsei CHOI

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14

    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

    SEMICONDUCTOR PACKAGE INCLUDING MOLDING LAYER
    4.
    发明公开
    SEMICONDUCTOR PACKAGE INCLUDING MOLDING LAYER 审中-公开

    公开(公告)号：US20240030161A1

    公开(公告)日：2024-01-25

    申请号：US18480660

    申请日：2023-10-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongho KIM ,  Jihwang KIM

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

    CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/3128 ,  H01L24/32 ,  H01L23/49838 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/73204

    Abstract: A semiconductor package including a semiconductor chip, a lower redistribution layer under the semiconductor chip, the lower redistribution layer including a lower insulating layer at a central region and at a portion of an edge region, and a trench at a remaining portion of the edge region, a plurality of outer connecting terminals under the lower redistribution layer, a molding layer including a first molding section and the second molding section, the first molding section being on the lower redistribution layer and surrounding a side surface of the semiconductor chip and the second molding section being in the trench and contacting a side surface of the lower insulating layer, and an upper redistribution layer on the molding layer may be provided. The side surface of the lower insulating layer and a side surface of the second molding section may be coplanar with each other.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230112061A1

    公开(公告)日：2023-04-13

    申请号：US17826505

    申请日：2022-05-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eunho CHO ,  Jihwang KIM ,  Jongbo SHIM

    IPC: H01L23/473 ,  H01L25/065 ,  H01L23/00

    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, a chip connection terminal configured to electrically connect the first semiconductor chip to the second semiconductor chip, an underfill layer disposed between the first semiconductor chip and the second semiconductor chip and surrounding the chip connection terminal, a vertical porous structure filling spaces of a plurality of vertical cooling channels passing through the first semiconductor chip, the second semiconductor chip, and the underfill layer in a vertical direction, and having a plurality of cooling holes, and a cooling fluid provided to the plurality of cooling holes of the vertical porous structure to flow inside the plurality of vertical cooling channels.

    INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    7.
    发明申请
    INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20220189835A1

    公开(公告)日：2022-06-16

    申请号：US17376883

    申请日：2021-07-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Choongbin YIM ,  Dongwook KIM ,  Hyunki KIM ,  Jongbo SHIM ,  Jihwang KIM ,  Sungkyu PARK ,  Yongkwan LEE ,  Byoungwook JANG

    IPC: H01L23/12 ,  H01L23/538

    Abstract: A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.

    SEMICONDUCTOR PACKAGE INCLUDING MOLDING LAYER
    9.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING MOLDING LAYER 有权

    公开(公告)号：US20220344279A1

    公开(公告)日：2022-10-27

    申请号：US17510749

    申请日：2021-10-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongho KIM ,  Jihwang KIM

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

    Abstract: A semiconductor package including a semiconductor chip, a lower redistribution layer under the semiconductor chip, the lower redistribution layer including a lower insulating layer at a central region and at a portion of an edge region, and a trench at a remaining portion of the edge region, a plurality of outer connecting terminals under the lower redistribution layer, a molding layer including a first molding section and the second molding section, the first molding section being on the lower redistribution layer and surrounding a side surface of the semiconductor chip and the second molding section being in the trench and contacting a side surface of the lower insulating layer, and an upper redistribution layer on the molding layer may be provided. The side surface of the lower insulating layer and a side surface of the second molding section may be coplanar with each other.

    SEMICONDUCTOR PACKAGES HAVING SUPPORTING MEMBERS
    10.
    发明申请
    SEMICONDUCTOR PACKAGES HAVING SUPPORTING MEMBERS 有权

    公开(公告)号：US20220173081A1

    公开(公告)日：2022-06-02

    申请号：US17370149

    申请日：2021-07-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taeseok CHOI ,  Jihwang KIM ,  Jongbo SHIM

    IPC: H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

    Abstract: A semiconductor package includes a lower substrate including a lower passivation layer, a lower pad, element pads and a supporting pad that are disposed on a lower surface of the lower substrate. The lower passivation layer partially covers the lower pad, the element pads and the supporting pad. A semiconductor chip is disposed on an upper surface of the lower substrate. An upper substrate is disposed on the semiconductor chip and is connected to the lower substrate. An encapsulator is disposed between the lower substrate and the upper substrate. An element is disposed on the lower surface of the lower substrate. The element is bonded to the element pads. A lower supporting member is disposed on the lower surface of the lower substrate. A supporting bonding member bonds the lower supporting member to the supporting pad.

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