MEMORY DEVICE, HOST DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE

    公开(公告)号:US20230138845A1

    公开(公告)日:2023-05-04

    申请号:US17810929

    申请日:2022-07-06

    Abstract: A memory device, a host device and a method of operating the memory device are provided. The memory device includes a data signal generator configured to provide a data signal to a transmission driver, the transmission driver configured to output a multi-level signal having any one of first to third signal levels based on the data signal, a command decoder configured to receive a feedback signal from outside of the memory device and decode the feedback signal, a data signal controller configured to adjust the data signal based on a decoding result of the command decoder, and a drive strength controller configured to adjust at least one of the first to third signal levels based on the decoding result of the command decoder.

    MEMORY DEVICE AND METHOD FOR CALIBRATING THE DEVICE AND FABRICATING THE DEVICE

    公开(公告)号:US20230143365A1

    公开(公告)日:2023-05-11

    申请号:US17852664

    申请日:2022-06-29

    CPC classification number: G11C7/1048 G11C2207/2254

    Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.

    MULTI-CHIP PACKAGE
    3.
    发明申请
    MULTI-CHIP PACKAGE 审中-公开

    公开(公告)号:US20200227131A1

    公开(公告)日:2020-07-16

    申请号:US16537970

    申请日:2019-08-12

    Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.

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