公开(公告)号：US20240212746A1

公开(公告)日：2024-06-27

申请号：US18541218

申请日：2023-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu JUNG ,  Jindo BYUN ,  Joohwan KIM ,  Eun Seok SHIN ,  Hyun-Yoon CHO ,  Junghwan CHOI

IPC: G11C11/4096 ,  G11C11/4093 ,  H03K19/017

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  H03K19/01742 ,  G11C2207/2254

Abstract: Disclosed is a memory device which includes a pull-up driver that is connected between a power supply voltage and a first node, a T-coil circuit that is connected between the first node and a second node, an external resistor, and a ZQ controller that performs a ZQ calibration operation on the pull-up driver. The ZQ controller includes a path selecting circuit that selects one node among the first node and the second node, a comparing circuit that compares a voltage of the one node selected by the path selecting circuit with a pull-up reference voltage and outputs a comparison result, and a code generating circuit that generates a pull-up code for driving the pull-up driver, based on the comparison result. While the pull-up code is generated, the external resistor is connected between the second node and a ground voltage.

公开(公告)号：US20210327476A1

公开(公告)日：2021-10-21

申请号：US17355765

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHUN LEE ,  Daesik MOON ,  Young-Soo SOHN ,  Young-Hoon SON ,  Ki-Seok OH ,  Changkyo LEE ,  Hyun-Yoon CHO ,  Kyung-Soo HA ,  Seokhun HYUN

IPC: G11C7/10 ,  G06F3/06

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US20230143365A1

公开(公告)日：2023-05-11

申请号：US17852664

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Hwan KIM ,  Jun Young PARK ,  Jin Do BYUN ,  Kwang Seob SHIN ,  Eun Seok SHIN ,  Hyun-Yoon CHO ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C2207/2254

Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.

公开(公告)号：US20220138045A1

公开(公告)日：2022-05-05

申请号：US17398158

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Young PARK ,  Young-Hoon SON ,  Hyun-Yoon CHO ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G06F11/10 ,  H03M13/29 ,  G06F1/08

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.