-
公开(公告)号：US11963361B2
公开(公告)日：2024-04-16
申请号：US17140277
申请日：2021-01-04
发明人： Changsun Hwang , Youngjin Kwon , Gihwan Kim , Hansol Seok , Dongseog Eun , Jongheun Lim
CPC分类号： H10B43/40 , H01L23/5226 , H10B41/27 , H10B41/41 , H10B43/27
摘要： An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.
-
公开(公告)号：US20240224533A1
公开(公告)日：2024-07-04
申请号：US18605115
申请日：2024-03-14
发明人： Changsun Hwang , Youngjin Kwon , Gihwan Kim , Hansol Seok , Dongseog Eun , Jongheun Lim
IPC分类号： H10B43/40 , H01L23/522 , H10B41/27 , H10B41/41 , H10B43/27
CPC分类号： H10B43/40 , H01L23/5226 , H10B41/27 , H10B41/41 , H10B43/27
摘要： An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.
-
公开(公告)号：US11417675B2
公开(公告)日：2022-08-16
申请号：US16903514
申请日：2020-06-17
发明人： Kiseok Jang , Chang-Sun Hwang , Chungki Min , Kieun Seo , Jongheun Lim
IPC分类号： H01L27/11573 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L21/768 , H01L27/11582 , H01L23/535 , H01L27/1157
摘要： A three-dimensional semiconductor memory device including a peripheral circuit structure on a first substrate, the peripheral circuit structure including peripheral circuits, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure including a plurality of electrodes that are stacked on the second substrate and a penetrating interconnection structure penetrating the electrode structure and the second substrate may be provided. The penetrating interconnection structure may include a lower insulating pattern, a mold pattern structure on the lower insulating pattern, a protection pattern between the lower insulating pattern and the mold pattern structure, and a penetration plug. The penetration plug may penetrate the mold pattern structure and the lower insulating pattern and may be connected to the peripheral circuit structure. The protection pattern may be at a level lower than that of the lowermost one of the electrodes.
-
公开(公告)号：US20220028877A1
公开(公告)日：2022-01-27
申请号：US17204380
申请日：2021-03-17
发明人： Changsun Hwang , Gihwan Kim , Hansol Seok , Jongheun Lim , Kiseok Jang
IPC分类号： H01L27/11573 , H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11582
摘要： An integrated circuit device includes a vertical stack of nonvolatile memory cells on a substrate, which are configured as a vertical NAND string of memory cells. This vertical stack of nonvolatile memory cells includes a plurality of gate patterns, which are spaced apart from each other by corresponding electrically insulating layers. A dummy mold structure is also provided on the substrate. The dummy mold structure includes a vertical stack of sacrificial layers, which are spaced apart from each other by corresponding electrically insulating layers. An insulation pattern is provided, which fills a dish-shaped recess in a first one of the sacrificial layers in the vertical stack of sacrificial layers. This insulation pattern has an upper surface that is coplanar with an upper surface of the first one of the sacrificial layers.
-
公开(公告)号：US11805655B2
公开(公告)日：2023-10-31
申请号：US17324411
申请日：2021-05-19
发明人： Donghoon Kwon , Junsuk Kim , Jongheun Lim
IPC分类号： H01L21/00 , H10B43/50 , H01L23/535 , H01L21/768 , H10B41/27 , H10B41/41 , H10B41/50 , H10B43/27 , H10B43/40
CPC分类号： H10B43/50 , H01L21/76805 , H01L21/76895 , H01L23/535 , H10B41/27 , H10B41/41 , H10B41/50 , H10B43/27 , H10B43/40
摘要： A memory device includes a cell stacked structure on a substrate, the cell stacked structure including insulation layers and gate patterns alternately stacked, a channel structure passing through the cell stacked structure, the channel structure extending in a vertical direction, a dummy structure on the substrate, the dummy structure being spaced apart from the cell stacked structure, and the dummy structure including insulation layers and metal patterns alternately stacked, a first through via contact passing through the dummy structure, the first through via contact extending in the vertical direction, and a first capping insulation pattern between a sidewall of the first through via contact and each of the metal patterns in the dummy structure, the first capping insulation pattern insulating the first through via contact from each of the metal patterns.
-
公开(公告)号：US11482448B2
公开(公告)日：2022-10-25
申请号：US17035827
申请日：2020-09-29
发明人： Hansol Seok , Chungki Min , Changsun Hwang , Gihwan Kim , Jongheun Lim
IPC分类号： H01L21/768 , H01L27/11582 , H01L23/522 , H01L23/528 , H01L23/535
摘要： Semiconductor devices and methods of forming the same are provided. The methods may include forming a stacked structure that may include a stacking area and a stepped area and may include first layers and second layers alternately stacked. The second layers may have a stepped shape in the stepped area, and the stepped area may include at least one flat area and at least one inclined stepped area. The methods may also include forming a capping insulating layer covering the stacked structure. The capping insulating layer may include a first capping region having a first upper surface and a second capping region having a second upper surface at a lower level than the first upper surface. The methods may further include patterning the capping insulating layer to form protrusions at least one of which overlaps the stepped area and then planarizing the capping insulating layer.
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.015 秒)
