公开(公告)号：US20220028877A1

公开(公告)日：2022-01-27

申请号：US17204380

申请日：2021-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changsun Hwang ,  Gihwan Kim ,  Hansol Seok ,  Jongheun Lim ,  Kiseok Jang

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: An integrated circuit device includes a vertical stack of nonvolatile memory cells on a substrate, which are configured as a vertical NAND string of memory cells. This vertical stack of nonvolatile memory cells includes a plurality of gate patterns, which are spaced apart from each other by corresponding electrically insulating layers. A dummy mold structure is also provided on the substrate. The dummy mold structure includes a vertical stack of sacrificial layers, which are spaced apart from each other by corresponding electrically insulating layers. An insulation pattern is provided, which fills a dish-shaped recess in a first one of the sacrificial layers in the vertical stack of sacrificial layers. This insulation pattern has an upper surface that is coplanar with an upper surface of the first one of the sacrificial layers.

公开(公告)号：US20240224533A1

公开(公告)日：2024-07-04

申请号：US18605115

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changsun Hwang ,  Youngjin Kwon ,  Gihwan Kim ,  Hansol Seok ,  Dongseog Eun ,  Jongheun Lim

IPC: H10B43/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.

公开(公告)号：US11963361B2

公开(公告)日：2024-04-16

申请号：US17140277

申请日：2021-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changsun Hwang ,  Youngjin Kwon ,  Gihwan Kim ,  Hansol Seok ,  Dongseog Eun ,  Jongheun Lim

IPC: H10B41/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.

公开(公告)号：US11640922B2

公开(公告)日：2023-05-02

申请号：US17578785

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso Shin ,  Chungki Min ,  Gihwan Kim ,  Sanghyeok Kim ,  Hyo-Jung Kim ,  Geunwon Lim

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/11573 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/311

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

公开(公告)号：US20240238935A1

公开(公告)日：2024-07-18

申请号：US18396918

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gihwan Kim ,  Donghoon Kwon ,  Kihoon Jang

IPC: B24B37/015

CPC classification number: B24B37/015

Abstract: A chemical mechanical polishing apparatus, may include: a turntable; a CMP pad installed on an upper surface of the turntable; a polishing head disposed above the turntable and contacting a wafer with the CMP pad to press the wafer; a slurry supply unit supplying slurry to the CMP pad; and a temperature control unit disposed between the slurry supply unit and the polishing head, wherein the temperature control unit may be provided with a body disposed above the CMP pad; and heating members disposed on a bottom surface of the body to heat the CMP pad, wherein the body may be provided with a suction port disposed between the heating members to suction steam.

公开(公告)号：US11889688B2

公开(公告)日：2024-01-30

申请号：US17509567

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Sun Hwang ,  Gihwan Kim ,  Chungki Min

IPC: H01L27/11556 ,  H10B41/27 ,  H01L29/66 ,  G11C5/02 ,  H01L25/07 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L25/074 ,  H01L29/66666 ,  H10B43/27

Abstract: A semiconductor device include; a substrate including a cell array region and a key region, a stack structure on the cell array region including vertically stacked electrodes, a dummy structure on the key region, a vertical channel structure penetrating the stack structure to connect the substrate, a dummy pillar penetrating the first dummy structure, an interlayer dielectric layer on the stack structure and the dummy structure, wherein an upper portion of the interlayer dielectric layer on the dummy structure includes a key pattern that vertically overlaps the dummy pillar, and a capping layer on the key region and covering the key pattern.

公开(公告)号：US11482448B2

公开(公告)日：2022-10-25

申请号：US17035827

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hansol Seok ,  Chungki Min ,  Changsun Hwang ,  Gihwan Kim ,  Jongheun Lim

IPC: H01L21/768 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming a stacked structure that may include a stacking area and a stepped area and may include first layers and second layers alternately stacked. The second layers may have a stepped shape in the stepped area, and the stepped area may include at least one flat area and at least one inclined stepped area. The methods may also include forming a capping insulating layer covering the stacked structure. The capping insulating layer may include a first capping region having a first upper surface and a second capping region having a second upper surface at a lower level than the first upper surface. The methods may further include patterning the capping insulating layer to form protrusions at least one of which overlaps the stepped area and then planarizing the capping insulating layer.

公开(公告)号：US11257708B2

公开(公告)日：2022-02-22

申请号：US16377516

申请日：2019-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso Shin ,  Chungki Min ,  Gihwan Kim ,  Sanghyeok Kim ,  Hyo-Jung Kim ,  Geunwon Lim

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/11573 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/311

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.