公开(公告)号：US20240261930A1

公开(公告)日：2024-08-08

申请号：US18536321

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yejin Choi ,  Donghoon Kwon

IPC: B24B37/015

CPC classification number: B24B37/015

Abstract: A substrate polishing apparatus includes a platen having a surface configured polish through relative movement between the platen and a semiconductor substrate, a slurry supply configured to supply slurry to the platen, wherein the slurry flows to a location between the semiconductor substrate and the platen, a substrate holder configured to grip and fix the semiconductor substrate to be in contact with the platen such that the platen contacts the surface of the semiconductor substrate to be polished, a temperature controller having a thermal conductive body that is configured to contact the surface of the platen to transfer heat between the thermal conductive body and the platen to control the temperature of the platen, and a first cleaner having an ultrasonic transducer and at least one probe, the ultrasonic transducer configured to generate ultrasonic waves and the probe configured to transmit the ultrasonic waves to an outer surface of the thermal conductive body.

公开(公告)号：US20240105417A1

公开(公告)日：2024-03-28

申请号：US18202155

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeoseon Choi ,  Donghoon Kwon

IPC: H01J37/20 ,  H01J37/26

CPC classification number: H01J37/20 ,  H01J37/261 ,  H01J2237/2007

Abstract: A sample holder includes a head, a first holding plate extending in a first direction from one surface of the head and including at least one first sample hole configured to accommodate at least one first sample and a first main surface configured such that the at least one first sample accommodated in the at least one first sample hole is exposed at the first main surface, and a second holding plate extending in the first direction from the one surface of the head and including at least one second sample hole configured to accommodate at least one second sample and a second main surface configured such that the at least one second sample accommodated in the at least one second sample hole is exposed at the second main surface, wherein a direction perpendicular to the first main surface of the first holding plate differs from a direction perpendicular to the second main surface of the second holding plate.

公开(公告)号：US20240431102A1

公开(公告)日：2024-12-26

申请号：US18414551

申请日：2024-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyeon Kim ,  Donghoon Kwon

IPC: H10B43/27 ,  H10B41/27

Abstract: A semiconductor device according to an embodiment includes: a gate stacking structure that comprises a first stacking structure and a second stacking structure on the first stacking structure, the first stacking structure and the second stacking structure each comprising a plurality of gate electrodes; a channel structure that extends into the gate stacking structure; and a plurality of gate contact portions that are respectively connected to the plurality of gate electrodes of a first pad area of the first stacking structure and a second pad area of the second stacking structure; where the first stacking structure comprises a buffer insulating portion that comprises a boundary portion that is adjacent to the second pad area, where the buffer insulating portion comprises a first section, a second section, and an inner section that is between the first section and the second section in a first direction.

公开(公告)号：US11744079B2

公开(公告)日：2023-08-29

申请号：US17473141

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Chang-Sun Hwang ,  Chungki Min

IPC: H01L23/535 ,  H10B43/50 ,  H01L23/00 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L23/535 ,  H01L23/562 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes an upper-level layer having a cell array region, a cell contact region and a dummy region on a substrate. The upper-level layer includes a semiconductor layer, a cell array structure including first and second stack structures sequentially stacked on the semiconductor layer of the cell array region, the first and second stack structures comprising stacked electrodes, a first staircase structure on the semiconductor layer of the cell contact region, the electrodes extending from the cell array structure into the first staircase structure such that the cell array structure is connected to the first staircase structure, a vertical channel structure penetrating the cell array structure, a dummy structure in the dummy region, the dummy structure at the same level as the second stack structure, the dummy structure including stacked first layers, and cell contact plugs in the cell contact region and connected to the first staircase structure.

公开(公告)号：US20230255031A1

公开(公告)日：2023-08-10

申请号：US18047376

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Boun Yoon ,  Kihoon Jang

IPC: H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11573 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device includes a peripheral circuit structure including a substrate, a circuit element on the substrate, connection patterns electrically connected to the circuit element, and a peripheral insulating structure on the circuit element, a memory cell structure on the peripheral circuit structure, the memory cell structure including interlayer insulating layers and gate electrodes alternately stacked on each other, an upper wiring, and a through-contact plug electrically connecting the upper wiring to an upper connection pattern in, which is in an uppermost position of the connection patterns relative to an upper surface of the substrate providing a base reference surface, wherein the peripheral circuit structure further includes a dam structure on the upper connection pattern, the peripheral insulating structure includes a first insulating layer on the circuit element and a side surface of the upper connection pattern and a second insulating layer, a capping layer, and a third insulating layer sequentially stacked on the first insulating layer, wherein the dam structure passes through the second insulating layer and contacts the upper connection pattern, and wherein the through-contact plug includes a lower portion passing through the dam structure and contacting the upper connection pattern and an upper portion on the lower portion.

公开(公告)号：US20250041996A1

公开(公告)日：2025-02-06

申请号：US18425770

申请日：2024-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkeun Cho ,  Donghoon Kwon

IPC: B24D7/06 ,  B24D18/00

Abstract: Disclosed are grinding wheels, back-grinding apparatuses, and abrasive article manufacturing methods. The grinding wheel comprises a wheel body having a disk shape and an abrasive article combined with one surface of the wheel body. The abrasive article includes an abrasive body and a plurality of grinding particles in the abrasive body. The abrasive body provides a groove hole that is recessed in a first direction as a horizontal direction on a lateral surface of the abrasive body. A length in the first direction of the groove hole is less than a width in the first direction of the abrasive body.

公开(公告)号：US20240290637A1

公开(公告)日：2024-08-29

申请号：US18237547

申请日：2023-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minseon Kim ,  Donghoon Kwon

IPC: H01L21/67 ,  A46B13/00 ,  A46B13/02

CPC classification number: H01L21/67046 ,  A46B13/001 ,  A46B13/008 ,  A46B13/02 ,  A46B2200/3073

Abstract: A brush assembly includes a first brush including a first body that is cylindrical, and a first vertical gear connected to a surface of the cylindrical first body that faces a third body, the first vertical gear being configured to rotate in a first vertical direction, a second brush including a first horizontal gear configured to rotate in a first horizontal direction and a second body connected to a lower portion of the first horizontal gear and rotatably connected to the first body, and a third brush including a second vertical gear connected to a surface of the third body that faces the first body, the second vertical gear being configured to rotate in a second vertical direction that is opposite to the first vertical direction, where the first horizontal gear is engaged with a lower portion of the first vertical gear.

公开(公告)号：US20230286108A1

公开(公告)日：2023-09-14

申请号：US17931948

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Hyojung Kim ,  Chungki Min ,  Kihoon Jang

IPC: B24B55/02 ,  B24B57/02 ,  B24B37/10 ,  B24B37/34 ,  B24B53/017

CPC classification number: B24B55/02 ,  B24B57/02 ,  B24B37/107 ,  B24B37/34 ,  B24B53/017

Abstract: A polishing apparatus for a substrate, includes: a platen having a polishing pad attached to an upper surface thereof, and configured to rotate in a rotational direction, a temperature control unit configured to spray a temperature control fluid onto the polishing pad, a slurry supply unit configured to supply a slurry to the polishing pad, a polishing head on the polishing pad, and configured to rotate a semiconductor substrate in contact with the polishing pad, and a first fence between the temperature control unit and the slurry supply unit extending from a center outwardly, along the rotational direction, to control a flow of the temperature control fluid, wherein the temperature control unit, the slurry supply unit, and the polishing head are sequentially positioned along the rotational direction.

公开(公告)号：US20240312902A1

公开(公告)日：2024-09-19

申请号：US18474345

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon

IPC: H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

Abstract: A three-dimensional semiconductor memory device comprises a first substrate including a cell array region and a contact region, a stack structure including interlayer dielectric layers and gate electrodes on the first substrate, a second dielectric layer on the stack structure, a cell contact plug that extends through the second dielectric layer and the contact region, a selection mold structure on the stack structure and the second dielectric layer, a third dielectric layer on the selection mold structure, and a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug. The dummy through contact has a second width. The capping through contact has a first width. The second width is different from the first width.

公开(公告)号：US20240298441A1

公开(公告)日：2024-09-05

申请号：US18476415

申请日：2023-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Jung Kim ,  Donghoon Kwon

IPC: H10B41/41 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B41/41 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device may include a peripheral circuit structure, a source structure on the peripheral circuit structure, a first capacitor electrode on the peripheral circuit structure, an electrode insulating layer that at least partially surrounds the first capacitor electrode, a gate stack on the source structure, a memory channel structure that extends through the gate stack, a staircase insulating layer on the gate stack and the electrode insulating layer, a second capacitor electrode on the first capacitor electrode and that extends through the staircase insulating layer, and a penetration via that extends through the staircase insulating layer and the electrode insulating layer.