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公开(公告)号：US20220028877A1
公开(公告)日：2022-01-27
申请号：US17204380
申请日：2021-03-17
发明人： Changsun Hwang , Gihwan Kim , Hansol Seok , Jongheun Lim , Kiseok Jang
IPC分类号： H01L27/11573 , H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11582
摘要： An integrated circuit device includes a vertical stack of nonvolatile memory cells on a substrate, which are configured as a vertical NAND string of memory cells. This vertical stack of nonvolatile memory cells includes a plurality of gate patterns, which are spaced apart from each other by corresponding electrically insulating layers. A dummy mold structure is also provided on the substrate. The dummy mold structure includes a vertical stack of sacrificial layers, which are spaced apart from each other by corresponding electrically insulating layers. An insulation pattern is provided, which fills a dish-shaped recess in a first one of the sacrificial layers in the vertical stack of sacrificial layers. This insulation pattern has an upper surface that is coplanar with an upper surface of the first one of the sacrificial layers.
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公开(公告)号：US11963361B2
公开(公告)日：2024-04-16
申请号：US17140277
申请日：2021-01-04
发明人： Changsun Hwang , Youngjin Kwon , Gihwan Kim , Hansol Seok , Dongseog Eun , Jongheun Lim
CPC分类号： H10B43/40 , H01L23/5226 , H10B41/27 , H10B41/41 , H10B43/27
摘要： An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.
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公开(公告)号：US11482448B2
公开(公告)日：2022-10-25
申请号：US17035827
申请日：2020-09-29
发明人： Hansol Seok , Chungki Min , Changsun Hwang , Gihwan Kim , Jongheun Lim
IPC分类号： H01L21/768 , H01L27/11582 , H01L23/522 , H01L23/528 , H01L23/535
摘要： Semiconductor devices and methods of forming the same are provided. The methods may include forming a stacked structure that may include a stacking area and a stepped area and may include first layers and second layers alternately stacked. The second layers may have a stepped shape in the stepped area, and the stepped area may include at least one flat area and at least one inclined stepped area. The methods may also include forming a capping insulating layer covering the stacked structure. The capping insulating layer may include a first capping region having a first upper surface and a second capping region having a second upper surface at a lower level than the first upper surface. The methods may further include patterning the capping insulating layer to form protrusions at least one of which overlaps the stepped area and then planarizing the capping insulating layer.
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公开(公告)号：US20240224533A1
公开(公告)日：2024-07-04
申请号：US18605115
申请日：2024-03-14
发明人： Changsun Hwang , Youngjin Kwon , Gihwan Kim , Hansol Seok , Dongseog Eun , Jongheun Lim
IPC分类号： H10B43/40 , H01L23/522 , H10B41/27 , H10B41/41 , H10B43/27
CPC分类号： H10B43/40 , H01L23/5226 , H10B41/27 , H10B41/41 , H10B43/27
摘要： An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.
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公开(公告)号：US20190081102A1
公开(公告)日：2019-03-14
申请号：US15919639
申请日：2018-03-13
发明人： Kichul Park , Ki-Woong Kim , Hansol Seok , Byoungho Kwon , Boun Yoon
IPC分类号： H01L27/22 , H01L23/522 , H01L43/08 , H01L43/02 , H01F10/32 , H01L23/532 , H01L23/528 , G11C11/16 , H01L43/12 , H01L21/768 , H01L21/027 , H01L21/3213
摘要： A semiconductor memory device may include a selection transistor on a semiconductor substrate, an interlayered insulating layer covering the selection transistor, a lower contact plug coupled to a drain region of the selection transistor and configured to penetrate the interlayered insulating layer, and a magnetic tunnel junction pattern coupled to the lower contact plug. The lower contact plug may include a metal pattern and a capping metal pattern in contact with a top surface of the metal pattern. The capping metal pattern may include a top surface having a surface roughness that is smaller than a surface roughness of the top surface of the metal pattern. The magnetic tunnel junction pattern may include bottom and top electrodes, a lower magnetic layer and an upper magnetic layer between the top and bottom electrodes, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.
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