公开(公告)号：US12283251B2

公开(公告)日：2025-04-22

申请号：US18368283

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-ju Lee ,  Kyoung Hwan Kwon ,  Soo Yong Kim ,  Sang Hoon Lee ,  Jun Ho Huh

IPC: G09G3/30 ,  G09G3/3275

Abstract: A display driver integrated circuit, System-On-Chip, and display system including the System-On-Chip are provided. A display driver integrated circuit (IC) includes: a clock generator configured to generate an internal operating clock; and a control circuit configured to provide a data signal to a pixel array based on the internal operating clock, wherein the data signal corresponds to frame data, wherein the control circuit is further configured to, in a frame data update period: receive first frame data, perform a first synchronization operation on the internal operating clock based on the first frame data, and provide a first data signal to the pixel array, and wherein the control circuit is further configured to, in a low power mode (LPM) period when an update of the frame data is not performed: transmit a sync request signal based on a result of monitoring a state of a display panel, receive a frequency signal from a System-on-Chip (SoC) in response to the sync request signal, and perform a second synchronization operation on the internal operating clock based on the frequency signal.

公开(公告)号：US20180013546A1

公开(公告)日：2018-01-11

申请号：US15677202

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Rang Jang ,  Suh Ho Lee ,  Tomas Scherrer ,  Jun Ho Huh ,  Chul Jin Kim

IPC: H04L7/04 ,  G06F13/42 ,  H04L7/00 ,  H04B1/16 ,  H04L7/033

CPC classification number: H04L7/048 ,  G06F13/4291 ,  H04B1/16 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0054 ,  H04L7/0087 ,  H04L7/0337 ,  H04L7/044

Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

公开(公告)号：US11244066B2

公开(公告)日：2022-02-08

申请号：US16824123

申请日：2020-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Hyun Kim ,  Jun Ho Huh

IPC: H04L29/06 ,  H04L9/32 ,  G06F21/62 ,  G06F13/16

Abstract: A system on chip includes a host controller and a secure controller for securing communication between the system on chip and external devices accessing a memory controlled by a memory and an encryption/decryption module for encrypting and decrypting the data.

公开(公告)号：US12282587B2

公开(公告)日：2025-04-22

申请号：US17894586

申请日：2022-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Ho Huh ,  Donguk Kim ,  Choonghoon Lee

IPC: G06F21/74 ,  G06F18/25 ,  G06F21/62 ,  G06N3/063

Abstract: An electronic device includes a memory and a processor. The memory stores information related to an artificial intelligence model that performs arithmetic operations through neural network layers. The processor pre-processes raw data and obtains output data by inputting the pre-processed raw data to the artificial intelligence model. First data used for pre-processing the raw data and second data used in a portion of the neural network layers are stored in a secure area of the memory, and third data used in remaining layers of the neural network layers other than the portion is stored in a non-secure area of the memory.

公开(公告)号：US09755821B2

公开(公告)日：2017-09-05

申请号：US15072470

申请日：2016-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Rang Jang ,  Suh Ho Lee ,  Tomas Scherrer ,  Jun Ho Huh ,  Chul Jin Kim

IPC: H04L7/00 ,  H04L7/04 ,  H04B1/16 ,  G06F13/42 ,  H04L7/033

CPC classification number: H04L7/048 ,  G06F13/4291 ,  H04B1/16 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0054 ,  H04L7/0087 ,  H04L7/0337 ,  H04L7/044

Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.