公开(公告)号：US20240310719A1

公开(公告)日：2024-09-19

申请号：US18532757

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyun HWANG ,  Jaeil LEE ,  Kyoungcho NA

IPC: G03F1/70 ,  G03F7/00 ,  H01L21/66

CPC classification number: G03F1/70 ,  G03F7/70504 ,  G03F7/70508 ,  G03F7/70516 ,  G03F7/706 ,  H01L22/12

Abstract: An overlay correction method for improving an overlay parameter of an ultra-high order component includes: obtaining misalignment components of an overlay through measurement; converting the misalignment components into overlay parameters; applying a conversion logic between the overlay parameters; converting the overlay parameters into aberration input data; and performing an exposure process by applying the aberration input data to an exposure machine, wherein the overlay parameters are divided into a first overlay parameter shifting in a first direction that is an extending direction of a slit, and a second overlay parameter shifting in a second direction that is perpendicular to the first direction, and the performing of the exposure process includes correcting the first and second overlay parameters including a higher-order component of a 3rd order or greater with respect to a location of the slit in the first direction.

公开(公告)号：US20230275032A1

公开(公告)日：2023-08-31

申请号：US18051639

申请日：2022-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeil LEE ,  Kyoungcho NA

IPC: H01L23/544 ,  H01L21/308

CPC classification number: H01L23/544 ,  H01L21/308 ,  H01L2223/54426

Abstract: A method of manufacturing a semiconductor device may determine rework of a photoresist pattern using an after-development inspection (ADI) of a semiconductor layer. The rework may include a single to dual conversion (SDC) of an overlay function.

公开(公告)号：US20230180475A1

公开(公告)日：2023-06-08

申请号：US17894524

申请日：2022-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmook CHOI ,  Jihong KIM ,  Kyoungcho NA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/14

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/14

Abstract: A method for manufacturing a semiconductor device including forming a first substrate and a second substrate thereon; forming a first stack region by alternately stacking first interlayer insulating and sacrificial layers on the second substrate; forming a second stack region by alternately stacking second interlayer insulating and sacrificial layers on the first stack region; forming first openings spaced apart from each other in the first direction by partially removing the second stack region; forming a first filling insulating layer in the first openings; forming a second opening by partially removing the second stack region between the first openings; removing the second sacrificial layers exposed through the second opening; forming a lower separation region including the first filling insulating layer and a second filling insulating layer, by forming the second filling insulating layer in the second opening and regions in which the second sacrificial layers have been removed.