公开(公告)号：US20250157921A1

公开(公告)日：2025-05-15

申请号：US18740739

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeewoong Kim ,  Seunghun Lee ,  Kyowook Lee ,  Keunhwi Cho

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

Abstract: Provided is an integrated circuit device with reduced line margins. The integrated circuit device includes an active area on a substrate, a channel area in the active area, a gate line that extends around the channel area, a plurality of first upper lines that electrically connect the channel area and the gate line to each other, a plurality of first lower lines of a side of the substrate, and a second lower wiring line on a side of the plurality of first lower lines that is opposite the substrate. The plurality of first lower lines includes a jog pattern line and an island pattern line that is spaced apart from the jog pattern line, and the island pattern line is electrically connected to the second lower wiring line by a lower contact.

公开(公告)号：US20240049438A1

公开(公告)日：2024-02-08

申请号：US18116107

申请日：2023-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun Lee ,  Seokhyeon Yoon ,  Kyowook Lee ,  Hyejin Lee

IPC: H10B10/00 ,  G11C11/412

CPC classification number: H10B10/12 ,  G11C11/412

Abstract: A semiconductor device includes a substrate, a SRAM cell including a pass-gate transistor, a pull-down transistor, and a pull-up transistor on substrate. The SRAM cell includes an active fin extending in a first direction, the pass-gate transistor and the pull-down transistor are disposed adjacent to each other on the active fin in the first direction, the pass-gate transistor includes first channel layers, a first gate electrode, first source/drain regions, and first inner spacers, the pull-down transistor includes second channel layers, a second gate electrode, second source/drain regions, and second inner spacers, and one of the first inner spacers and one of the second inner spacers are disposed on the same height level and have different thicknesses in the first direction.

公开(公告)号：US20240321886A1

公开(公告)日：2024-09-26

申请号：US18605400

申请日：2024-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghee Cho ,  Myungil Kang ,  Kyungho Kim ,  Kyowook Lee ,  Seunghun Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A stacked integrated circuit device includes a plurality of transistors including a pair of pull-up transistors in a first layer, a pair of pull-down transistors in a second layer that is at a different vertical level than the first layer, and a pair of pass-gate transistors in the first or second layer, a contact configured to electrically connect a source/drain region of one of the pull-up transistors, a source/drain region of one of the pull-down transistors, and a source/drain region of one of the pass-gate transistors to one another, a gate contact configured to connect a gate electrode of the other pull-up transistor to a gate electrode of the other pull-down transistor, and an upper wire on the contact and the gate contact, the upper wire extending in a first horizontal direction and being connected to the contact and the gate contact.