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    INTEGRATED CIRCUIT DEVICE
    1.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20250157921A1

    公开(公告)日：2025-05-15

    申请号：US18740739

    申请日：2024-06-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeewoong Kim ,  Seunghun Lee ,  Kyowook Lee ,  Keunhwi Cho

    IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

    Abstract: Provided is an integrated circuit device with reduced line margins. The integrated circuit device includes an active area on a substrate, a channel area in the active area, a gate line that extends around the channel area, a plurality of first upper lines that electrically connect the channel area and the gate line to each other, a plurality of first lower lines of a side of the substrate, and a second lower wiring line on a side of the plurality of first lower lines that is opposite the substrate. The plurality of first lower lines includes a jog pattern line and an island pattern line that is spaced apart from the jog pattern line, and the island pattern line is electrically connected to the second lower wiring line by a lower contact.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240365527A1

    公开(公告)日：2024-10-31

    申请号：US18521209

    申请日：2023-11-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeewoong Kim ,  Kyung Hee Cho

    IPC: H10B10/00

    CPC classification number: H10B10/125

    Abstract: A semiconductor memory device includes a substrate including a first surface and a second surface, which are opposite to each other, a lower active region on the first surface, the lower active region including a lower gate electrode and a lower active contact, which are spaced apart from each other, an upper active region stacked on the lower active region, the upper active region including an upper gate electrode and an upper active contact, which are spaced apart from each other, a first metal layer on the first surface, and a back-side metal layer on the second surface. The back-side metal layer includes a first shared pad electrically connecting the lower gate electrode to the lower active contact. The first metal layer includes a second shared pad electrically connecting the upper gate electrode to the upper active contact.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250169048A1

    公开(公告)日：2025-05-22

    申请号：US18671559

    申请日：2024-05-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jeewoong Kim ,  Kyo-Wook Lee ,  Seunghun Lee ,  Keun Hwi Cho

    IPC: H10B10/00 ,  G11C11/412 ,  G11C11/419 ,  H01L23/485 ,  H01L29/417

    Abstract: A semiconductor device may include a first lower active contact, a first source/drain pattern on the first lower active contact, a second lower active contact, a second source/drain pattern on the second lower active contact, a lower conductive layer electrically connected to the first and second lower active contacts, a third source/drain pattern and a fourth source/drain pattern between the first and second source/drain patterns, a first upper active contact on the third source/drain pattern, a second upper active contact on the fourth source/drain pattern, and an upper conductive line electrically connected to the first and second upper active contacts. The first to fourth source/drain patterns, the first and second lower active contacts, and the first and second upper active contacts may be disposed between the lower conductive layer and upper conductive line.

    INTEGRATED CIRCUIT
    6.
    发明公开
    INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20240088200A1

    公开(公告)日：2024-03-14

    申请号：US18321817

    申请日：2023-05-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeewoong Kim ,  Hojun Kim ,  Taiko Yamaguchi

    IPC: H01L27/08 ,  H01F27/28 ,  H01F27/29 ,  H01L23/522 ,  H01L23/58

    CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01F27/29 ,  H01L23/5227 ,  H01L23/585

    Abstract: An integrated circuit including an inductive element according to some embodiments is provided. The inductive element includes a first through electrode extending in a first direction that is perpendicular to a substrate (e.g., an upper surface of the substrate), an upper metallization pattern connected to the first through electrode and extending in a second direction that is perpendicular to the first direction, and a lower metallization pattern connected to the first through electrode and extending in the second direction, wherein the upper metallization pattern and the lower metallization pattern are spaced apart from each other with the first through electrode therebetween.

    SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE AND SEPARATION STRUCTURE
    7.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE AND SEPARATION STRUCTURE 审中-公开

    公开(公告)号：US20240079467A1

    公开(公告)日：2024-03-07

    申请号：US18296209

    申请日：2023-04-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jeewoong Kim ,  Jisu Kang ,  Hojun Kim

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

    Abstract: A semiconductor device includes active regions, including a first active region and a second active region, extending in a first horizontal direction, an isolation region defining the active regions, a gate structure disposed on the isolation region and extending in a second horizontal direction to intersect the active region, and separation structures penetrating through the gate structure and disposed on the isolation region between the first active region and the second active region. The separation structures include a first separation structure extending into the isolation region, and a second separation structure disposed on the first separation structure and penetrating through at least a portion of the first separation structure, and a width of a lower region of the second separation structure in the second horizontal direction is less than a width of an upper region of the first separation structure in the second horizontal direction.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    8.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240072117A1

    公开(公告)日：2024-02-29

    申请号：US18307259

    申请日：2023-04-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gukhee Kim ,  Kyoungwoo Lee ,  Jeewoong Kim ,  Sangcheol Na ,  Minchan Gwak ,  Youngwoo Kim ,  Anthony Dongick Lee

    IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088

    CPC classification number: H01L29/0847 ,  H01L21/823475 ,  H01L27/088

    Abstract: A semiconductor device includes a substrate having a first and second active patterns therein, first and second source/drain patterns extending on the first and second active patterns, respectively, and an active contact on the first and second source/drain patterns. An upper contact is provided, which extends from the active contact towards the substrate, and between the first and second active patterns. A lower power interconnection line is provided, which is buried in a lower portion of the substrate and includes: a buried interconnection portion having a line shape, and a lower contact portion extending vertically from the buried interconnection portion to a bottom surface of the upper contact. A barrier pattern is provided, which extends between the lower contact portion and the upper contact, but not between the buried interconnection portion and the lower contact portion.

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