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公开(公告)号：US11728388B2
公开(公告)日：2023-08-15
申请号：US17694994
申请日：2022-03-15
发明人： Keunhwi Cho , Byounghak Hong , Myunggil Kang
IPC分类号： H01L29/161 , H01L29/10 , H01L29/78
CPC分类号： H01L29/161 , H01L29/1041 , H01L29/7848
摘要： A semiconductor device including an active structure on a substrate, the active structure including silicon germanium patterns and silicon patterns alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on sidewalls of the active structure that face in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source/drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction that is perpendicular to the first direction, wherein the silicon germanium patterns are silicon rich-silicon germanium.
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公开(公告)号：US20220406919A1
公开(公告)日：2022-12-22
申请号：US17575856
申请日：2022-01-14
发明人： Beomjin PARK , Myunggil Kang , Dongwon Kim , Keunhwi Cho
摘要： A semiconductor device includes: an active region extending on a substrate in a first direction; a plurality of semiconductor layers spaced apart from each other vertically on the active region, including a lower semiconductor layer and an uppermost semiconductor layer disposed above the lower semiconductor layer and having a thickness greater than that of the lower semiconductor layer; a gate structure extending on the substrate in a second direction, perpendicular to the first direction, and including a gate electrode at least partially surrounding each of the plurality of semiconductor layers; a spacer structure disposed on both sidewalls of the gate structure; and source/drain regions disposed on the active region on both sides of the gate structure and contacting the plurality of semiconductor layers.
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公开(公告)号：US11948942B2
公开(公告)日：2024-04-02
申请号：US18122253
申请日：2023-03-16
发明人： Minhee Choi , Keunhwi Cho , Myunggil Kang , Seokhoon Kim , Dongwon Kim , Pankwi Park , Dongsuk Shin
IPC分类号： H01L29/08 , H01L21/02 , H01L27/092 , H01L29/06 , H01L29/161 , H01L29/167 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/78
CPC分类号： H01L27/0924 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/0673 , H01L29/0847 , H01L29/161 , H01L29/167 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/7851
摘要： An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1−xGex layer, where x≠0, and the inner blocking layer including a Si layer.
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公开(公告)号：US20230120496A1
公开(公告)日：2023-04-20
申请号：US18046656
申请日：2022-10-14
发明人： Keunhwi Cho , Gibum Kim , Myunggil Kang , Dongwon Kim
IPC分类号： H01L29/786 , H01L27/092 , H01L29/06 , H01L29/775 , H01L29/423 , H01L29/49
摘要： A semiconductor device includes a substrate, an active fin on the substrate, and a transistor on the active fin. The transistor includes a lower channel layer, an intermediate channel layer, and an upper channel layer sequentially stacked, and a gate structure traversing the active fin, respectively surrounding the channel layers, and including a gate dielectric and a gate electrode. The gate electrode includes a lower electrode portion between the active fin and the lower channel layer, an intermediate electrode portion between the lower channel layer and the intermediate channel layer, and an upper electrode portion between the intermediate channel layer and the upper channel layer. The gate electrode includes a work function adjusting metal element, and a content of the work function adjusting metal element in the lower electrode portion is different from that in each of the intermediate electrode portion and the upper electrode portion.
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公开(公告)号：US20230131215A1
公开(公告)日：2023-04-27
申请号：US17863741
申请日：2022-07-13
发明人： Keunhwi Cho , Jinkyu Kim , Myunggil Kang , Dongwon Kim , Kisung Suh
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/417 , H01L29/78
摘要： A method of manufacturing a semiconductor device includes forming a semiconductor structure extending from a substrate in a first direction and having first and second regions; forming a sacrificial gate pattern intersecting the first region of the semiconductor structure and extending in a second direction perpendicular to the first direction; reducing a width in the second direction of the second region of the semiconductor structure exposed to at least one side of the sacrificial gate pattern; forming at least one recess portion by removing a portion of the second region of the semiconductor structure; forming one or more source/drain regions in the recess portion of the semiconductor structure on at least one side of the sacrificial gate pattern; forming at least one gap region by removing the sacrificial gate pattern; and forming a gate structure by depositing a gate dielectric layer and a gate electrode in the gap region.
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公开(公告)号：US11631674B2
公开(公告)日：2023-04-18
申请号：US17231114
申请日：2021-04-15
发明人： Minhee Choi , Keunhwi Cho , Myunggil Kang , Seokhoon Kim , Dongwon Kim , Pankwi Park , Dongsuk Shin
IPC分类号： H01L27/092 , H01L29/06 , H01L29/66 , H01L29/78
摘要： An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.
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公开(公告)号：US11282928B2
公开(公告)日：2022-03-22
申请号：US15931964
申请日：2020-05-14
发明人： Keunhwi Cho , Byounghak Hong , Myunggil Kang
IPC分类号： H01L29/161 , H01L29/10 , H01L29/78
摘要： A semiconductor device including an active structure on a substrate, the active structure including silicon germanium patterns and silicon patterns alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on sidewalls of the active structure that face in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source/drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction that is perpendicular to the first direction, wherein the silicon germanium patterns are silicon rich-silicon germanium.
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