公开(公告)号：US20240282773A1

公开(公告)日：2024-08-22

申请号：US18645551

申请日：2024-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyeon Yoon ,  Junyoung Park ,  Woocheol Shin ,  Seunghun Lee

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L27/1222 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/78696

Abstract: An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.

公开(公告)号：US20220208790A1

公开(公告)日：2022-06-30

申请号：US17410325

申请日：2021-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyeon Yoon ,  Junyoung Park ,  Woocheol Shin ,  Seunghun Lee

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H01L29/08

Abstract: An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.

公开(公告)号：US20240049438A1

公开(公告)日：2024-02-08

申请号：US18116107

申请日：2023-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun Lee ,  Seokhyeon Yoon ,  Kyowook Lee ,  Hyejin Lee

IPC: H10B10/00 ,  G11C11/412

CPC classification number: H10B10/12 ,  G11C11/412

Abstract: A semiconductor device includes a substrate, a SRAM cell including a pass-gate transistor, a pull-down transistor, and a pull-up transistor on substrate. The SRAM cell includes an active fin extending in a first direction, the pass-gate transistor and the pull-down transistor are disposed adjacent to each other on the active fin in the first direction, the pass-gate transistor includes first channel layers, a first gate electrode, first source/drain regions, and first inner spacers, the pull-down transistor includes second channel layers, a second gate electrode, second source/drain regions, and second inner spacers, and one of the first inner spacers and one of the second inner spacers are disposed on the same height level and have different thicknesses in the first direction.

公开(公告)号：US20240006485A1

公开(公告)日：2024-01-04

申请号：US18196081

申请日：2023-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhyeon Yoon ,  Taehyeon Kim ,  Seunghun Lee ,  Hyeongrae Kim

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L29/66545 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/42392

Abstract: A semiconductor device include first and second active patterns, first and second gate structures, and first and second source/drain layers. The first and second active patterns extend on the first and second regions in a first direction. The first and second gate structures are formed on the first and second active patterns, and extend in a second direction. The first and second source/drain layers are formed on the first and second active patterns adjacent to the first and second gate structures. The first active pattern includes a first well having first and second impurity regions. The second active pattern includes a second well having third and fourth impurity regions. A width in the second direction of the first impurity region is greater than that of the second impurity region. A width in the second direction of the third impurity region is smaller than that of the fourth impurity region.

公开(公告)号：US11973082B2

公开(公告)日：2024-04-30

申请号：US17410325

申请日：2021-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyeon Yoon ,  Junyoung Park ,  Woocheol Shin ,  Seunghun Lee

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L27/1222 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/78696

Abstract: An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.

公开(公告)号：US11881509B2

公开(公告)日：2024-01-23

申请号：US17396942

申请日：2021-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junbeom Park ,  Sangmo Koo ,  Minyi Kim ,  Seokhyeon Yoon

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/1033 ,  H01L29/66553

Abstract: The semiconductor device may include an active pattern provided on a substrate and a source/drain pattern on the active pattern. The source/drain pattern may include a bottom surface in contact with a top surface of the active pattern. The semiconductor device may further include a channel pattern connected to the source/drain pattern, a gate electrode extended to cross the channel pattern, and a fence insulating layer extended from a side surface of the active pattern to a lower side surface of the source/drain pattern. A pair of middle insulating patterns may be at both sides of the bottom surface of the source/drain pattern and between the active pattern and the source/drain pattern in contact with an inner side surface of the fence insulating layer.