公开(公告)号：US20170062572A1

公开(公告)日：2017-03-02

申请号：US15132800

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Su Yoo ,  WeonHong KIM ,  Moonkyun SONG ,  Minjoo LEE ,  Soojung CHOI

IPC: H01L29/40 ,  H01L21/441 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/441 ,  H01L21/762 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes forming a sacrificial gate pattern on an active pattern, forming spacers on opposite sidewalls of the sacrificial gate pattern, forming an interlayer insulating layer on the active pattern and the spacers, removing the sacrificial gate pattern to form a gate trench that exposes a region of the active pattern, forming a gate dielectric layer on the region of the active pattern exposed by the gate trench, performing a first heat treatment at a pressure of less than 1 atm to remove impurities in the interlayer insulating layer, performing a second heat treatment on the gate dielectric layer at a temperature greater than a temperature of the first heat treatment, and forming a gate electrode in the gate trench.

Abstract translation: 形成半导体器件的方法包括在有源图案上形成牺牲栅极图案，在牺牲栅极图案的相对侧壁上形成间隔物，在有源图案和间隔物上形成层间绝缘层，去除牺牲栅极图案以形成 栅极沟槽，其暴露有源图案的区域，在由栅极沟槽暴露的有源图案的区域上形成栅极电介质层，在小于1atm的压力下进行第一热处理以去除层间绝缘层中的杂质 在大于第一热处理的温度的温度下对栅介质层进行第二热处理，以及在栅沟中形成栅电极。

公开(公告)号：US20230146530A1

公开(公告)日：2023-05-11

申请号：US18052726

申请日：2022-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangeun LEE ,  Minjoo LEE ,  Eunyoung LEE ,  Minsik KIM

IPC: H01L27/06 ,  H01L21/02 ,  H10B12/00

CPC classification number: H01L27/0605 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10888

Abstract: An integrated circuit device according may include a plurality of gate structures embedded in a substrate, a direct contact on the substrate between the plurality of gate structures, and a bit line electrode layer on the direct contact. The bit line electrode layer has a thickness of about 10 nm to 30 nm. The bit line electrode layer may include a molybdenum tungsten (MoW) alloy including molybdenum (Mo) a range of about 25 at % to about 75 at %.

公开(公告)号：US20220262738A1

公开(公告)日：2022-08-18

申请号：US17475506

申请日：2021-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jangeun LEE ,  Minjoo LEE ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An integrated circuit chip includes a base layer. A first wiring layer is disposed on the base layer and includes a plurality of first wiring structures. A second wiring layer is disposed on the first wiring layer and includes a plurality of second wiring structures. Each of the plurality of second wiring structures has a first metal layer and a second metal layer respectively having different resistivities. A third wiring layer is disposed on the second wiring layer and includes a plurality of third wiring structures. Each of the plurality of first wiring structures comprises Ru, Mo, W, or an alloy thereof. Each of the plurality of second wiring structures comprises Ru, Mo, W, or an alloy thereof. Each of the plurality of third wiring structures comprises a material different from a material of the plurality of first wiring structures.