公开(公告)号：US20240266291A1

公开(公告)日：2024-08-08

申请号：US18479211

申请日：2023-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyoung LEE ,  Wei GUO ,  Wulin HE ,  Buseo CHOI ,  Sanghyun PARK ,  Wonwoong CHUNG

IPC: H01L23/532 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53219 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/5329

Abstract: A material including an alloy including aluminum of 99% by weight to 99.8% by weight, copper of 0.1% by weight to 0.5% by weight, and scandium of 0.1% by weight to 0.5% by weight, a metal line in a semiconductor device including the material, and a method for forming the metal line in the semiconductor device may be provided.

公开(公告)号：US20230146530A1

公开(公告)日：2023-05-11

申请号：US18052726

申请日：2022-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangeun LEE ,  Minjoo LEE ,  Eunyoung LEE ,  Minsik KIM

IPC: H01L27/06 ,  H01L21/02 ,  H10B12/00

CPC classification number: H01L27/0605 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10888

Abstract: An integrated circuit device according may include a plurality of gate structures embedded in a substrate, a direct contact on the substrate between the plurality of gate structures, and a bit line electrode layer on the direct contact. The bit line electrode layer has a thickness of about 10 nm to 30 nm. The bit line electrode layer may include a molybdenum tungsten (MoW) alloy including molybdenum (Mo) a range of about 25 at % to about 75 at %.

公开(公告)号：US20180174802A1

公开(公告)日：2018-06-21

申请号：US15804304

申请日：2017-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungkyu LIM ,  DOUGYONG SUNG ,  Myoung Soo PARK ,  Jaehoon KIM ,  Eunyoung LEE ,  Seiwon CHUNG ,  YOSHIHISA HIRANO

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32119 ,  H01J37/3211 ,  H01J37/32183 ,  H01J37/32642 ,  H01J2237/334 ,  H01L21/67069 ,  H01L21/6831

Abstract: A dielectric window, a plasma system including the same, a method of fabricating the same, and a method of manufacturing a semiconductor device are provided. The method of manufacturing the semiconductor device may include steps of providing a substrate in a plasma chamber, performing a plasma treatment on a surface of the substrate, and removing the substrate from the plasma chamber, wherein the plasma chamber comprises the dielectric window. The dielectric window may include a dielectric material disk with at least one void, a filler filled in the void to allow the dielectric material disk to have a flat surface, and a passivation layer provided on the filler and the dielectric material disk.

公开(公告)号：US20240194604A1

公开(公告)日：2024-06-13

申请号：US18357403

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyoung LEE ,  Wonwoong CHUNG ,  Buseo CHOI ,  Kkotchorong PARK ,  Seulgi BAE ,  Uisuk JUNG ,  Dong-Chan LIM

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53223 ,  H01L21/76864 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266

Abstract: The described technology relates generally to a material for a metal line in a semiconductor device including an alloy including aluminum as a main material, copper, and an element X, wherein the element X has 1) a coefficient of thermal expansion (CTE) of greater than about 0.55 ppm/K and less than about 5 ppm/K, 2) a melting point (MP) of greater than about 3000° C., and 3) electronegativity of greater than about 2.2, a metal line in a semiconductor device including the alloy, and a method of forming a metal line in a semiconductor device.