Semiconductor package
    1.
    发明授权

    公开(公告)号:US12237250B2

    公开(公告)日:2025-02-25

    申请号:US17498893

    申请日:2021-10-12

    Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20230056041A1

    公开(公告)日:2023-02-23

    申请号:US17706978

    申请日:2022-03-29

    Abstract: A semiconductor package includes: a base substrate including a lower redistribution layer; a lower semiconductor chip including a first active surface and on the base substrate; an upper semiconductor chip including a second active surface on the lower semiconductor chip and having an area larger than that of the lower semiconductor chip; an intermediate connection member including an upper redistribution layer on the second active surface of the upper semiconductor chip between the lower and upper semiconductor chips; a plurality of vertical interconnectors disposed around the lower semiconductor chip on the base substrate and connecting the lower redistribution layer and the upper redistribution layer; and a molding portion on the base substrate and including a first portion surrounding the lower semiconductor chip and the vertical interconnectors, and a second portion extending upwardly from the first portion and on side surfaces of the upper semiconductor chip and the intermediate connection member.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请

    公开(公告)号:US20220077048A1

    公开(公告)日:2022-03-10

    申请号:US17329256

    申请日:2021-05-25

    Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

    Semiconductor package including outer conductive plate

    公开(公告)号:US12300625B2

    公开(公告)日:2025-05-13

    申请号:US17828799

    申请日:2022-05-31

    Abstract: A semiconductor package includes a substrate; and a first semiconductor device and a second semiconductor device that are provided on the substrate. The substrate includes a first dielectric layer and a second dielectric layer provided on the first dielectric layer, a plurality of signal lines provided between the first dielectric layer and the second dielectric layer and connecting the first semiconductor device to the second semiconductor device, and a conductive pad and a conductive plate provided on the second dielectric layer. The conductive pad overlaps the first semiconductor device or the second semiconductor device. The conductive plate overlaps the signal lines.

    Method for preloading application and electronic device supporting same

    公开(公告)号:US12265835B2

    公开(公告)日:2025-04-01

    申请号:US18322919

    申请日:2023-05-24

    Abstract: An electronic device may include: a housing including a first housing and a second housing movable with respect to the first housing; a flexible display in which a display area for displaying a screen is expanded or reduced as the second housing moves with respect to the first housing; a memory; and a processor, wherein the processor is configured to: identify a change in the size of the display area on the basis of the movement of the second housing relative to the first housing; determine an application to be preloaded from among a plurality of applications on the basis of the identified size of the display area; load, into the memory, a preload process including some of resources for executing the determined application to be preloaded; and, in response to the occurrence of an event associated with the execution of the application to be preloaded, load an activity for the execution of the application by using the loaded preload process.

    Semiconductor package including a dummy pattern

    公开(公告)号:US12211777B2

    公开(公告)日:2025-01-28

    申请号:US17731416

    申请日:2022-04-28

    Abstract: A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.

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