公开(公告)号：US12015018B2

公开(公告)日：2024-06-18

申请号：US18060853

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong Hwang ,  Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

公开(公告)号：US12261106B2

公开(公告)日：2025-03-25

申请号：US17535093

申请日：2021-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package comprises a first redistribution substrate including first interconnection layers sequentially stacked on each other, a semiconductor chip mounted on the first redistribution substrate, a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip, a second redistribution substrate disposed on the mold layer and including second interconnection layers sequentially stacked on each other, a connection terminal disposed beside the semiconductor chip to connect the first and second redistribution substrates to each other, and outer terminals disposed on a bottom surface of the first redistribution substrate. Each of the first and second interconnection layers may include an insulating layer and a wire pattern in the insulating layer. The first redistribution substrate may have substantially the same thickness as the second redistribution substrate, and the first interconnection layers may be thinner than the second interconnection layers.

公开(公告)号：US20230019311A1

公开(公告)日：2023-01-19

申请号：US17731416

申请日：2022-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  Dongkyu Kim ,  Jongyoun Kim ,  Hyeonjeong Hwang

IPC: H01L23/498 ,  H01L25/10

Abstract: A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.

公开(公告)号：US12191236B2

公开(公告)日：2025-01-07

申请号：US17533606

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Minjung Kim ,  Dongkyu Kim ,  Taewon Yoo

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/49 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.

公开(公告)号：US20240347435A1

公开(公告)日：2024-10-17

申请号：US18748765

申请日：2024-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Kyounglim SUK ,  Seokhyun LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204

Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

公开(公告)号：US12040264B2

公开(公告)日：2024-07-16

申请号：US17508250

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Kyounglim Suk ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204

Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

公开(公告)号：US20240136250A1

公开(公告)日：2024-04-25

申请号：US18197998

申请日：2023-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho Jang ,  Inhyung Song ,  Kyungdon Mun ,  Hyeonjeong Hwang

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/3738 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/165 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: The present disclosure provides semiconductor packages including a heat dissipation structure. In some embodiments, the semiconductor package includes a package substrate, a stacked chip disposed on the package substrate and including a lower chip and an upper chip, a memory chip disposed on the package substrate adjacent to the stacked chip, and an encapsulant encapsulating at least a portion of the stacked chip and the memory chip on the package substrate. An upper surface of the upper chip is exposed from the encapsulant. A dummy silicon chip is in contact with the upper chip on the lower chip.

公开(公告)号：US12261104B2

公开(公告)日：2025-03-25

申请号：US17670635

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Dongkyu Kim ,  Minjung Kim ,  Yeonho Jang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package including a redistribution substrate extending in a first direction and a second direction perpendicular to the first direction, a semiconductor chip mounted on a top surface of the redistribution substrate, and an outer terminal on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, a redistribution insulating layer covering a top surface and a side surface of the under-bump pattern, a protection pattern interposed between the top surface of the under-bump pattern and the redistribution insulating layer, and interposed between the side surface of the under-bump pattern and the redistribution insulating layer, and a redistribution pattern on the under-bump pattern. The outer terminal may be disposed on a bottom surface of the under-bump pattern.

公开(公告)号：US20250029906A1

公开(公告)日：2025-01-23

申请号：US18646834

申请日：2024-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyounglim Suk ,  Kimin Cheong ,  Hyeonjeong Hwang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/00 ,  H01L25/18

Abstract: Provided are a semiconductor package including a pad with high reliability and a method of manufacturing the semiconductor package. The semiconductor package includes a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a through post extending around the semiconductor chip and on the first redistribution substrate, and a second redistribution substrate on the semiconductor chip and the through post. A first pad region and a second pad region are defined on an upper surface of the second redistribution substrate, the first pad region positioned at a central portion of the second redistribution substrate, and the second pad region extending around the first pad region, a first-type pad in a planar shape is in a first opening, a second-type pad having an outer protruding portion is in a second opening.

公开(公告)号：US20240120280A1

公开(公告)日：2024-04-11

申请号：US18214341

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Shanghoon Seo ,  Jihwang Kim ,  Sangjin Baek ,  Hyeonjeong Hwang

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5383 ,  H01L21/561 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/06 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2924/19106

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor device mounted on the first redistribution structure, a molding layer surrounding the first semiconductor device, a second redistribution structure disposed on the molding layer and the first semiconductor device, a plurality of vertical connection conductors vertically extending in the molding layer and electrically connecting the first redistribution pattern to the second redistribution pattern, a second semiconductor device mounted on the second redistribution structure, the second semiconductor device and the first semiconductor device vertically and partially overlapping each other, a heat dissipation pad structure contacting an upper surface of the first semiconductor device, and a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device along a first straight line extending in a horizontal direction that is parallel to the upper surface of the first semiconductor device.