公开(公告)号：US12009274B2

公开(公告)日：2024-06-11

申请号：US17358149

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eungkyu Kim ,  Kyounglim Suk

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes; a wiring structure including signal wiring and heat transfer wiring, an active chip on the wiring structure, a signal terminal disposed between the wiring structure and the active chip, a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring, a passive chip on the wiring structure, a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring, and a heat spreader on the passive chip.

公开(公告)号：US20220302002A1

公开(公告)日：2022-09-22

申请号：US17498893

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Minjung Kim ,  Kyounglim Suk ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/29

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

公开(公告)号：US20250079249A1

公开(公告)日：2025-03-06

申请号：US18791760

申请日：2024-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom Ko ,  Kyounglim Suk ,  Jaegun Shin ,  Sanghoon Lee ,  Woojin Jang ,  Gwangjae Jeon

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L25/18

Abstract: A semiconductor package includes a buffer die, an intermediate core die stack on the buffer die, where the intermediate core die stack includes a plurality of intermediate core dies and a plurality of first gap filling portions that respectively overlap side surfaces of the plurality of intermediate core dies in a first direction, a top core die on the intermediate core die stack, and a second gap filling portion that overlaps side surfaces of the intermediate core die stack in the first direction and side surfaces of the top core die in the first direction.

公开(公告)号：US12040264B2

公开(公告)日：2024-07-16

申请号：US17508250

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Kyounglim Suk ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204

Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

公开(公告)号：US12237250B2

公开(公告)日：2025-02-25

申请号：US17498893

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Minjung Kim ,  Kyounglim Suk ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

公开(公告)号：US20240186231A1

公开(公告)日：2024-06-06

申请号：US18520453

申请日：2023-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwang KIM ,  Joonsung KIM ,  Sangjin Baek ,  Kyounglim Suk

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/181

Abstract: A semiconductor package includes a lower redistribution structure. A semiconductor device is disposed on the lower redistribution structure. A lower encapsulant is disposed on the lower redistribution structure and surrounds a side surface of the semiconductor device. An upper composite redistribution structure is disposed on an upper portion of the semiconductor device and includes a primary conductive structure, a secondary conductive structure disposed on the primary conductive structure, connection vias disposed between the primary conductive structure and the secondary conductive structure, and an upper encapsulant disposed between the primary conductive structure and the secondary conductive structure and surrounding the connection vias.

公开(公告)号：US20240096773A1

公开(公告)日：2024-03-21

申请号：US18319135

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Kyounglim Suk ,  Yeonho Jang ,  Hyeonjeong Hwang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05093 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/16227 ,  H01L2924/1434

Abstract: A semiconductor package includes a redistribution structure in which at least one redistribution layer and at least one insulating layer are alternately stacked; a semiconductor chip electrically connected to the at least one redistribution layer; and bumps on the redistribution structure, wherein the redistribution structure includes vias extending from the at least one redistribution layer in a vertical stacking direction of the redistribution structure; and under bump metallurgy (UBM) structures electrically connected between the vias and the bumps and configured to face the bumps in the vertical stacking direction of the redistribution structure, wherein each of the UBM structures includes a first UBM layer including a first metal material or an alloy of the first metal material; and a second UBM layer between one of the bumps and the first UBM layer and including a second metal material.

公开(公告)号：US20240071894A1

公开(公告)日：2024-02-29

申请号：US18335336

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Dongkyu Kim ,  Kyounglim Suk ,  Hyeonseok Lee

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

Abstract: A packaged integrated circuit includes a redistribution layer having a plurality of electrically conductive vias extending at least partially therethrough, and a plurality of lower pads electrically connected to corresponding ones of the plurality of electrically conductive vias. A semiconductor chip is provided on the redistribution layer, and external connection terminals are provided, which electrically contact corresponding ones of the plurality of lower pads within the redistribution layer. Each of the plurality of lower pads includes: (i) a lower under-bump metallization (UBM) layer in contact with a corresponding external connection terminal, and (ii) an upper UBM layer extending on and contacting the lower UBM layer. In addition, an upper surface of the lower UBM layer has a greater lateral width dimension relative to an upper surface of the upper UBM layer, which contacts a corresponding electrically conductive via.

公开(公告)号：US11670629B2

公开(公告)日：2023-06-06

申请号：US17190689

申请日：2021-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seho You ,  Kyounglim Suk

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L23/66

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/66 ,  H01L24/20 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16227

Abstract: A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.

公开(公告)号：US20220165778A1

公开(公告)日：2022-05-26

申请号：US17363931

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Kim ,  Dongkyu Kim ,  Kyounglim Suk ,  Jaegwon Jang ,  Hyeonjeong Hwang

IPC: H01L27/146

Abstract: An image sensor package includes a glass substrate configured to focus incident light, a first redistribution layer and a second redistribution layer both disposed under the glass substrate while being horizontally spaced apart from each other by a first distance, an image sensor disposed such that an upper surface thereof is vertically spaced apart from both a lower surface of the first redistribution layer and a lower surface of the second redistribution layer by a second distance, and a first connector that connects both the first redistribution layer and the second redistribution layer to the image sensor. The thickness of the glass substrate is 0.6 to 0.8 mm. The first distance is smaller than the horizontal length of the image sensor by 50 μm to 1 mm. The second distance is equal to or less than 0.1 mm.