公开(公告)号：US20220122908A1

公开(公告)日：2022-04-21

申请号：US17348936

申请日：2021-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donguk KWON ,  Jiwon SHIN ,  Kwangbok WOO ,  Minseung JI

IPC: H01L23/498 ,  H01L23/32 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: A lower semiconductor package of a package-on-package type semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate; a chip connecting terminal disposed between the semiconductor chip and the package substrate and configured to connect the semiconductor chip to the package substrate; conductive pillars arranged on the package substrate to at least partially surround the semiconductor chip; and a dam structure configured to cover the conductive pillars on the package substrate and having a first opening at least partially surrounding the semiconductor chip.

公开(公告)号：US20240153898A1

公开(公告)日：2024-05-09

申请号：US18387656

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Minseung JI ,  Seungduk Baek ,  Aenee Jang

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05676 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06152 ,  H01L2224/06181 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565

Abstract: A semiconductor package includes a lower chip including a first lower bonding pad and a second lower bonding pad, and an upper chip disposed on the lower chip, the upper chip including a first upper bonding pad and a second upper bonding pad respectively hybrid-bonded together. The first lower and upper bonding pads have a first shape in which first and second axis lengths are the same, and are disposed in a first center region of the chips. The second lower and upper bonding pads have a second shape in which third and fourth axis lengths differ, and are disposed in a first edge region which is near a corner point of the chip. In the second lower and upper bonding pads disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point.