公开(公告)号：US20190007062A1

公开(公告)日：2019-01-03

申请号：US15639475

申请日：2017-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MOSHE TWITTO ,  MOSHE BEN ARI ,  AVNER DOR ,  ELONA EREZ ,  JUN JIN KONG ,  YARON SHANY

IPC: H03M13/15 ,  H03M13/29 ,  H03M13/00

CPC classification number: H03M13/152 ,  H03M13/1515 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/2948 ,  H03M13/356 ,  H03M13/3707 ,  H03M13/616 ,  H03M13/617

Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises Δt syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1; and multiplying s by a right submatrix Ũ of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=Ũ·s.

公开(公告)号：US20170161202A1

公开(公告)日：2017-06-08

申请号：US14957114

申请日：2015-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： ELONA EREZ ,  AVNER DOR ,  JUN JIN KONG

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/10 ,  G06F3/06 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7207

Abstract: A data storage device includes a flash memory that includes blocks of physical pages that include physical sectors configured to store data therein. A memory control unit, including a flash translation layer (FTL), is configured to receive write data sectors to be stored in the flash memory, determine at least one matched data sector by matching a write data sector with a reference data sector based upon a deduplication operation, and store the reference data sector corresponding to the matched data sector in a physical sector of a physical page of a block in the flash memory. Logical-to-physical addresses of the reference data sector and the corresponding matched data sector are mapped in the FTL, and physical-to-logical information regarding the corresponding matched data sector is written in a designated physical-to-logical information area of the flash memory. The physical-to-logical information area may be a metadata area of a physical sector, an adjacent physical sector in a same page, a last sector of a block or a dedicated block of the flash memory.

公开(公告)号：US20190114228A1

公开(公告)日：2019-04-18

申请号：US15730943

申请日：2017-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MOSHE TWITTO ,  YARON SHANY ,  AVNER DOR ,  ELONA EREZ ,  JUN JIN KONG

IPC: G06F11/10 ,  G06F3/06 ,  H03M13/15 ,  H03M13/29

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F11/1072 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/29 ,  H03M13/2906

Abstract: A method of encoding generalized concatenated error-correcting codes includes providing a parity Matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n−{tilde over (k)}j, where the first n−kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix Rj of dimension (n−{tilde over (k)}j)(n−{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n−kl columns and Tj has k1−{tilde over (k)} columns; finding a vector c=(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n−{tilde over (k)}j; and solving ( A | I )  ( a b ) = ( Q j | T j )  s ~ = T j  s where a=0 and b=Tjs, and codeword c is nonzero only on the last n−{tilde over (k)}j=n−kj bits.

公开(公告)号：US20180136865A1

公开(公告)日：2018-05-17

申请号：US15352037

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MICHAEL ERLIHSON ,  SHMUEL DASHEVSKY ,  ELONA EREZ ,  GUY INBAR ,  JUN JIN KONG ,  KEON SOO HA

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0626 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0866 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/152 ,  G06F2212/214 ,  G06F2212/466 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7208

Abstract: A memory system includes a table storing a plurality of entries, where each entry is associated with a different logical block address (LBA), a plurality of memory devices, channels, and ways, where each memory device is connected to one of the channels ways and to one of the ways, and a memory controller configured to receive an LBA and data from a host, execute a plurality of pseudo-random functions on the received LBA to generate a plurality of slot indexes, select one of the slot indexes, write the data to one of the memory devices identified by the selected one slot index, and update a corresponding one of the entries to include the selected one slot index.

公开(公告)号：US20180102168A1

公开(公告)日：2018-04-12

申请号：US15288443

申请日：2016-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： IDDO NAISS ,  NOAM LIVNE ,  ELONA EREZ ,  JUN JIN KONG

IPC: G11C11/56 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C11/5642 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C29/52

Abstract: A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.

公开(公告)号：US20190050343A1

公开(公告)日：2019-02-14

申请号：US15671855

申请日：2017-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： ELONA EREZ ,  AVNER DOR ,  JUN-JIN KONG

IPC: G06F12/1009 ,  G06F3/06

Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

公开(公告)号：US20170160978A1

公开(公告)日：2017-06-08

申请号：US14956715

申请日：2015-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： ELONA EREZ ,  AVNER DOR ,  JUN JIN KONG

IPC: G06F3/06

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/00 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10

Abstract: A flash memory device includes physical pages that store data sectors therein. The method of operating the flash memory device includes receiving write data sectors to be stored in the flash memory device, pairing the write data sectors with write data sectors and with written data sectors previously stored in physical pages of the flash memory device based upon a matching and deduplication operation to define data sector pairs and a difference therebetween, and rewriting to the physical pages of the flash memory device, in a partial-page writing mode, to store the difference between the write data sector and its respective paired data sector. The partial-page writing mode is performed on a respective physical page after a previous programming and before erasing. The written data sectors included in the data sector pairs only partially occupy the corresponding physical page of the flash memory device. The difference between the write data sector and its respective paired data sector is stored in an unoccupied portion of the corresponding physical page of the flash memory device.

公开(公告)号：US20170149451A1

公开(公告)日：2017-05-25

申请号：US14949458

申请日：2015-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YARON SHANY ,  AVNER DOR ,  ELONA EREZ ,  JUN JIN KONG

IPC: H03M13/15 ,  H03M13/19 ,  H03M13/00

CPC classification number: G06F3/0641 ,  G06F3/0608 ,  G06F11/1453 ,  G06F17/30156 ,  H03M13/136 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1575 ,  H03M13/19 ,  H03M13/611

Abstract: A method, executed by a processor, for determining similarity between messages includes calculating a syndrome of each of first and second messages with respect to a linear code. A difference between the syndromes of the first and second messages is calculated, and a vector that minimizes a metric in a coset defined by the syndrome difference is identified. A compact representation of the second message that is based upon the first message is generated when a metric of the identified vector is less than or equal to a predetermined threshold. The compact representation of the second message is stored in a location of a memory device assigned for storing the second message, when the metric of the identified vector is less than or equal to the predetermined threshold.