公开(公告)号：US20220293154A1

公开(公告)日：2022-09-15

申请号：US17496003

申请日：2021-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-HOON JANG ,  KYUNGRYUN KIM ,  YOUNG JU KIM ,  SEUNG-JUN LEE ,  YOUNGBIN LEE ,  YEONKYU CHOI

IPC: G11C8/18 ,  G11C7/10

Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.

公开(公告)号：US20240161810A1

公开(公告)日：2024-05-16

申请号：US18381115

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG-JUN LEE ,  YOUNGHUN SEO ,  Hoseok Lee

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4087 ,  G11C11/4097

Abstract: A memory device includes a memory cell array which includes a plurality of word lines and a plurality of bit lines; a plurality of column selection lines which extends over the memory cell array and includes a first part of the memory cell array and a second part connected to the first part; a plurality of bit line sense amplifiers each connected to a bit line and configured to sense data stored in a memory cell; a plurality of local sense amplifiers each configured to output the sensed data from one of the bit line sense amplifiers through a column selection transistor connected to a local column selection line; a control logic circuit which generates a row address signal indicating an activation word line and a column address signal indicating an activation bit line; and a column decoder which activates a column selection line based on the column address signal.

公开(公告)号：US20230386542A1

公开(公告)日：2023-11-30

申请号：US18447950

申请日：2023-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-HOON JANG ,  KYUNGRYUN KIM ,  YOUNG JU KIM ,  SEUNG-JUN LEE ,  YOUNGBIN LEE ,  YEONKYU CHOI

IPC: G11C8/18 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/1045 ,  G11C7/1093 ,  G11C7/1066

Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.

公开(公告)号：US20240329045A1

公开(公告)日：2024-10-03

申请号：US18742453

申请日：2024-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-HOON JANG ,  KYUNGRYUN KIM ,  YOUNG JU KIM ,  SEUNG-JUN LEE ,  YOUNGBIN LEE ,  YEONKYU CHOI

IPC: G01N33/574 ,  G01N33/50

CPC classification number: G01N33/574 ,  G01N33/5091

Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.