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公开(公告)号：US20220085026A1
公开(公告)日：2022-03-17
申请号：US17229942
申请日：2021-04-14
发明人： HYOSUB KIM , KEUNNAM KIM , MANBOK KIM , SOOJEONG KIM , CHULKWON PARK , SEUNGBAE JEON , YOOSANG HWANG
IPC分类号： H01L27/108
摘要： Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.
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公开(公告)号：US20190325930A1
公开(公告)日：2019-10-24
申请号：US16460284
申请日：2019-07-02
发明人： SUNGWOO KIM , BONG-SOO KIM , YOUNGBAE KIM , KIJAE HUR , GWANHYEOB KOH , HYEONGSUN HONG , YOOSANG HWANG
IPC分类号： G11C11/00 , G11C5/02 , G11C14/00 , H01L27/108 , H01L23/528 , H01L27/24 , H01L49/02 , H01L45/00
摘要： A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.
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公开(公告)号：US20210043722A1
公开(公告)日：2021-02-11
申请号：US16860136
申请日：2020-04-28
发明人： JAE-HWAN CHO , SANGHO LEE , YOOSANG HWANG
IPC分类号： H01L49/02
摘要： Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.
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公开(公告)号：US20210020495A1
公开(公告)日：2021-01-21
申请号：US17039431
申请日：2020-09-30
发明人： Myeong-Dong LEE , KEUNNAM KIM , Dongryul LEE , Minseong CHOI , Jimin CHOI , YONG KWAN KIM , CHANGHYUN CHO , YOOSANG HWANG
IPC分类号： H01L21/768 , H01L27/108 , H01L23/532 , H01L23/535
摘要： According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
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公开(公告)号：US20210296321A1
公开(公告)日：2021-09-23
申请号：US17202465
申请日：2021-03-16
发明人： INKYOUNG HEO , HYO-SUB KIM , SOHYUN PARK , TAEJIN PARK , SEUNG-HEON LEE , YOUN-SEOK CHOI , SUNGHEE HAN , YOOSANG HWANG
IPC分类号： H01L27/108 , H01L23/532 , H01L21/768
摘要： A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.
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公开(公告)号：US20190325960A1
公开(公告)日：2019-10-24
申请号：US16458594
申请日：2019-07-01
发明人： SUNGWOO KIM , BONG-SOO KIM , YOUNGBAE KIM , KIJAE HUR , GWANHYEOB KOH , HYEONGSUN HONG , YOOSANG HWANG
摘要： A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.
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公开(公告)号：US20190252386A1
公开(公告)日：2019-08-15
申请号：US16268748
申请日：2019-02-06
发明人： KISEOK LEE , BONG-SOO KIM , JIYOUNG KIM , HUI-JUNG KIM , SEOKHAN PARK , HUNKOOK LEE , YOOSANG HWANG
IPC分类号： H01L27/108 , H01L23/528 , H01L29/08 , H01L29/10 , H01L29/165
CPC分类号： H01L27/10805 , H01L23/5226 , H01L23/528 , H01L27/10897 , H01L28/60 , H01L29/0847 , H01L29/1037 , H01L29/165
摘要： Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.
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公开(公告)号：US20210057419A1
公开(公告)日：2021-02-25
申请号：US16833919
申请日：2020-03-30
发明人： DONGSUK SHIN , JIYOUNG KIM , HOKYUN AN , CHAN MIN LEE , EUNJU CHO , HUI-JUNG KIM , JOONGCHAN SHIN , TAEHYUN AN , HYUNGEUN CHOI , YOOSANG HWANG , KISEOK LEE
IPC分类号： H01L27/108
摘要： A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.
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公开(公告)号：US20190333918A1
公开(公告)日：2019-10-31
申请号：US16509820
申请日：2019-07-12
发明人： Daeik KIM , SEMYEONG JANG , JEMIN PARK , YOOSANG HWANG
IPC分类号： H01L27/108 , H01L21/28 , H01L29/792 , H01L21/71
摘要： A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.
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公开(公告)号：US20190157133A1
公开(公告)日：2019-05-23
申请号：US16238172
申请日：2019-01-02
发明人： Myeong-Dong LEE , KEUNNAM KIM , Dongryul LEE , Minseong CHOI , Jimin CHOI , YONG KWAN KIM , CHANGHYUN CHO , YOOSANG HWANG
IPC分类号： H01L21/768 , H01L23/535 , H01L27/108 , H01L23/532
CPC分类号： H01L21/7682 , H01L21/76805 , H01L21/76849 , H01L21/76895 , H01L23/5329 , H01L23/535 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876
摘要： According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
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