公开(公告)号：US20250079265A1

公开(公告)日：2025-03-06

申请号：US18457311

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheol NA ,  Kyoung Woo Le ,  Min Chan Gwak ,  Guk Hee Kim ,  Beom Jin Kim ,  Young Woo Kim ,  Anthony Dongick Lee ,  Myeong Gyoon Chae

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate that includes a first surface and a second surface, a first source/drain pattern disposed on the first surface of the substrate, a second source/drain pattern disposed on the first surface of the, a first source/drain contact disposed on the first source/drain pattern and connected to the first source/drain pattern, a second source/drain contact disposed on the second source/drain pattern and connected to the second source/drain pattern, a rear wiring line disposed on the second surface of the substrate, a first contact connection via that connects the rear wiring line with the first source/drain contact, a second contact connection via that connects the rear wiring line with the second source/drain contact and is spaced apart from the first contact connection via, and an air gap structure disposed between the first contact connection via and the second contact connection via.

公开(公告)号：US20240203831A1

公开(公告)日：2024-06-20

申请号：US18486416

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anthony Dongick LEE ,  Min Chan GWAK ,  Guk Hee KIM ,  Young Woo KIM ,  Jin Kyu KIM ,  Sang Cheol NA ,  Yun Suk NAM ,  Kyoung Woo LEE ,  Hidenobu FUKUTOME

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5286 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13

Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a power delivery network layer; an insulating layer on the power delivery network layer and having an opening therein; a semiconductor layer filling the opening and covering the insulating layer; a first through-via extending through the semiconductor layer and electrically connected to the power delivery network layer; a second through-via extending through the insulating layer and the semiconductor layer and electrically connected to the power delivery network layer; a logic element on the semiconductor layer and electrically connected to the first through-via; and a passive element on the semiconductor layer and electrically connected to the second through-via.

公开(公告)号：US20230178477A1

公开(公告)日：2023-06-08

申请号：US17866917

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anthony Dongick LEE ,  Sang Cheol NA ,  Seo Woo NAM ,  Ki Chul PARK

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53238

Abstract: A semiconductor device is provided. The semiconductor device comprises a first wiring structure which includes a first material, and has a first width on a lowest surface in a first direction and a second wiring structure which includes a second material, is spaced apart from the first wiring structure in the first direction, and has a second width smaller than the first width on a lowest surface in the first direction, wherein a highest surface of the first wiring structure has a third width smaller than the first width in the first direction, and a highest surface of the second wiring structure has a fourth width smaller than the second width in the first direction.

公开(公告)号：US20240339540A1

公开(公告)日：2024-10-10

申请号：US18386898

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Jin KIM ,  Guk Hee KIM ,  Young Woo KIM ,  Jun Soo KIM ,  Sang Cheol NA ,  Kyoung Woo LEE ,  Anthony Dongick LEE ,  Min Seung LEE ,  Myeong Gyoon CHAE ,  Seung Seok HA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7855 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on an upper surface of the substrate, a field insulating layer surrounding a sidewall of the active pattern on the upper surface of the substrate, a first gate electrode extending in a second horizontal direction intersecting the first horizontal direction on the active pattern, a source/drain region disposed on at least one side of the first gate electrode on the active pattern, an upper interlayer insulating layer covering the source/drain region on the field insulating layer, a through via penetrating through the substrate, the field insulating layer and the upper interlayer insulating layer in a vertical direction, the through via spaced apart from the source/drain region in the second horizontal direction, a source/drain contact disposed inside the upper interlayer insulating layer on at least one side of the first gate electrode, the source/drain contact connected to the source/drain region, and a connection portion disposed inside the upper interlayer insulating layer, the connection portion connected to each of the through via and the source/drain contact, wherein a width of the connection portion in the first horizontal direction is greater than a width of the source/drain contact in the first horizontal direction.

公开(公告)号：US20230326831A1

公开(公告)日：2023-10-12

申请号：US18127895

申请日：2023-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheol NA ,  Kyoung Woo LEE ,  Min Chan GWAK ,  Guk Hee KIM ,  Young Woo KIM ,  Anthony Dongick LEE

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L23/481 ,  H01L29/66545 ,  H01L29/41733 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392

Abstract: A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.