公开(公告)号：US20230402382A1

公开(公告)日：2023-12-14

申请号：US18113715

申请日：2023-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Kyu KIM ,  Yun Suk NAM ,  Kyoung Woo LEE ,  Ho-Jun KIM ,  Da Rong OH ,  Sung Moon LEE ,  Hag Ju CHO ,  Seung Min CHA

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/66439 ,  H01L29/42392

Abstract: A semiconductor device includes: a base substrate; a first interlayer insulating layer disposed on the base substrate; a power rail disposed inside the first interlayer insulating layer; an active pattern extended in a first horizontal direction and disposed on the first interlayer insulating layer; a gate electrode extended in a second horizontal direction different from the first horizontal direction and disposed on the active pattern; a gate cut extended in the first horizontal direction and disposed on the power rail, wherein the gate cut separates the gate electrode; and a power rail via disposed inside the gate cut, wherein the power rail via is overlapped by the power rail.

公开(公告)号：US20240203831A1

公开(公告)日：2024-06-20

申请号：US18486416

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anthony Dongick LEE ,  Min Chan GWAK ,  Guk Hee KIM ,  Young Woo KIM ,  Jin Kyu KIM ,  Sang Cheol NA ,  Yun Suk NAM ,  Kyoung Woo LEE ,  Hidenobu FUKUTOME

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5286 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13

Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a power delivery network layer; an insulating layer on the power delivery network layer and having an opening therein; a semiconductor layer filling the opening and covering the insulating layer; a first through-via extending through the semiconductor layer and electrically connected to the power delivery network layer; a second through-via extending through the insulating layer and the semiconductor layer and electrically connected to the power delivery network layer; a logic element on the semiconductor layer and electrically connected to the first through-via; and a passive element on the semiconductor layer and electrically connected to the second through-via.

公开(公告)号：US20190330781A1

公开(公告)日：2019-10-31

申请号：US16462113

申请日：2017-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Hee RYU ,  Kyoung Woo LEE ,  Dong-Won KIM ,  Yongjie JIN ,  Jun Hong PARK

IPC: D06F37/26 ,  D06F25/00 ,  D06F58/26 ,  D06F58/02

Abstract: Disclosed is a washing machine including a drying function. Here, a height of a bottom end of a dryer disposed above a tub is lower than a height of a top end of the tub to have a space for integrating other devices having additional functions above the tub.

公开(公告)号：US20240339540A1

公开(公告)日：2024-10-10

申请号：US18386898

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Jin KIM ,  Guk Hee KIM ,  Young Woo KIM ,  Jun Soo KIM ,  Sang Cheol NA ,  Kyoung Woo LEE ,  Anthony Dongick LEE ,  Min Seung LEE ,  Myeong Gyoon CHAE ,  Seung Seok HA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7855 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on an upper surface of the substrate, a field insulating layer surrounding a sidewall of the active pattern on the upper surface of the substrate, a first gate electrode extending in a second horizontal direction intersecting the first horizontal direction on the active pattern, a source/drain region disposed on at least one side of the first gate electrode on the active pattern, an upper interlayer insulating layer covering the source/drain region on the field insulating layer, a through via penetrating through the substrate, the field insulating layer and the upper interlayer insulating layer in a vertical direction, the through via spaced apart from the source/drain region in the second horizontal direction, a source/drain contact disposed inside the upper interlayer insulating layer on at least one side of the first gate electrode, the source/drain contact connected to the source/drain region, and a connection portion disposed inside the upper interlayer insulating layer, the connection portion connected to each of the through via and the source/drain contact, wherein a width of the connection portion in the first horizontal direction is greater than a width of the source/drain contact in the first horizontal direction.

公开(公告)号：US20230326831A1

公开(公告)日：2023-10-12

申请号：US18127895

申请日：2023-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheol NA ,  Kyoung Woo LEE ,  Min Chan GWAK ,  Guk Hee KIM ,  Young Woo KIM ,  Anthony Dongick LEE

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L23/481 ,  H01L29/66545 ,  H01L29/41733 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392

Abstract: A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.

公开(公告)号：US20200219808A1

公开(公告)日：2020-07-09

申请号：US16441042

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soon Gyu HWANG ,  Kyoung Woo LEE ,  YoungWoo CHO ,  IL SUP KIM ,  Su Hyun BARK ,  Young-Ju PARK ,  Jong Min BAEK ,  Min HUH

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

公开(公告)号：US20200051909A1

公开(公告)日：2020-02-13

申请号：US16285583

申请日：2019-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Young KIM ,  Kyu Hee HAN ,  Sung Bin PARK ,  Yeong Gil KIM ,  Jong Min BAEK ,  Kyoung Woo LEE ,  Deok Young JUNG

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768

Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.