公开(公告)号：US10346087B2

公开(公告)日：2019-07-09

申请号：US15678759

申请日：2017-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-hoon Woo ,  Hak-sun Kim ,  Kwang-jin Lee ,  Su-chang Jeon

IPC: G11C16/04 ,  G06F3/06 ,  G06F13/16 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/32 ,  G11C7/10

Abstract: An apparatus for outputting an internal state of a memory apparatus and a memory system using the apparatus are provided. The apparatus includes a state signal generating circuit that generates a first signal indicating an internal operation state of the memory apparatus, and a state signal output control circuit that receives the first signal and outputs a second signal to an output pad based on a chip enable signal or an initially set function command, or both. The first signal indicates one state from among two states and the second signal indicates one state from among three states.

公开(公告)号：US11003382B2

公开(公告)日：2021-05-11

申请号：US16503116

申请日：2019-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-hoon Woo ,  Hak-sun Kim ,  Kwang-Jin Lee ,  Su-chang Jeon

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/32 ,  G11C7/10 ,  G11C16/04

Abstract: A memory system is provided and includes memory chips and a memory controller. Each of the memory chips one or more first state output pins arranged therein. The memory controller has arranged therein a first state input pin connected in a wired-AND configuration to the one or more first state output pins arranged in the memory chips. The memory controller is configured to transmit a chip enable signal and/or an initially set function command to the memory chips. Each of the memory chips outputs a first state signal having one level from among three logic levels according to a first internal operation state of the memory chip to the one or more first state output pins of the memory chip based on the chip enable signal and/or the initially set function command.

公开(公告)号：US10863134B2

公开(公告)日：2020-12-08

申请号：US15878083

申请日：2018-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-il Kang ,  Kwang-youn Kim ,  Seong-hoon Woo ,  Du-hee Jang ,  Hyun-young Jang ,  Shin-wook Choi

IPC: G08B5/36 ,  H04N5/655 ,  H04N5/64 ,  H05K5/02 ,  G06F1/16 ,  H04N5/63

Abstract: A display device is provided, which includes a display main body, a support configured to support the display main body, and the support being made of a transparent material, and a stand coupled to a lower portion of the support, wherein the display main body is configured to receive a power supply through the stand and the support.

公开(公告)号：US11847339B2

公开(公告)日：2023-12-19

申请号：US17231734

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-hoon Woo ,  Hak-sun Kim ,  Kwang-jin Lee ,  Su-chang Jeon

IPC: G06F13/00 ,  G06F3/06 ,  G06F13/16 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/32 ,  G11C7/10 ,  G11C16/04

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/16 ,  G11C7/1063 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/32 ,  G11C16/0483

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

公开(公告)号：US09158617B2

公开(公告)日：2015-10-13

申请号：US14048751

申请日：2013-10-08

Applicant: Samsung Electronics Co., Ltd

Inventor： Young-jin Cho ,  Eui-hyeok Kwon ,  Hak-sun Kim ,  Hyunsik Kim ,  Jae-geun Park ,  Seong-hoon Woo ,  Chul-seung Lee

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09

CPC classification number: G06F11/10 ,  G06F11/1012 ,  G06F11/1076 ,  G06F2211/109 ,  H03M13/09

Abstract: Performing a write operation or a read operation in a memory system may include compressing data of a first size unit, generating a plurality of types of Error Checking and Correction (ECC) information based on the compressed data, combining the compressed data and the plurality of types of ECC information in units of a second size, and writing the information combined in units of the second size into a memory device.

Abstract translation: 在存储器系统中执行写入操作或读取操作可以包括压缩第一尺寸单元的数据，基于压缩数据生成多种类型的错误检查和校正（ECC）信息，将压缩数据与多个 ECC信息的类型以第二大小为单位，并将以第二大小为单位组合的信息写入到存储装置中。