-
公开(公告)号：US11348876B2
公开(公告)日：2022-05-31
申请号：US17130505
申请日：2020-12-22
发明人： Kyoung Lim Suk , Seung-Kwan Ryu , Seokhyun Lee
IPC分类号： H01L21/00 , H01L23/538 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/00 , H01L25/10 , H01L25/00 , H01L21/683 , H01L23/498
摘要： A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.
-
公开(公告)号：US11217503B2
公开(公告)日：2022-01-04
申请号：US16748061
申请日：2020-01-21
发明人： Yang Gyoo Jung , Chul Woo Kim , Hyo-Chang Ryu , Seung-Kwan Ryu , Yun Seok Choi
IPC分类号： H01L23/367 , H01L23/42 , H01L25/10 , H01L25/065 , H01L23/498 , H05K1/18 , H01L23/00
摘要： A semiconductor package includes a substrate and an interposer disposed on the substrate. The interposer comprises a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction orthogonal to an upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction that is parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.
-
公开(公告)号：US09972580B2
公开(公告)日：2018-05-15
申请号：US15345779
申请日：2016-11-08
发明人： Yonghwan Kwon , Seung-Kwan Ryu
IPC分类号： H01L23/00 , H01L21/3105 , H01L21/56 , H01L23/31 , H01L23/538
CPC分类号： H01L23/562 , H01L21/31058 , H01L21/565 , H01L21/568 , H01L23/3121 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/29147 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2924/18162 , H01L2924/3511 , H01L2924/3512 , H01L2924/37001 , H01L2224/83
摘要： A semiconductor package includes a stack structure, a mold layer disposed on at least one sidewall of the stack structure, a redistribution line electrically connected to the stack structure, and an external terminal electrically connected to the redistribution line. The stack structure includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface. A dummy substrate is disposed on the non-active surface of the semiconductor chip. An adhesive layer is disposed between the dummy substrate and the semiconductor chip. The mold layer includes a top surface adjacent to the redistribution line and a bottom surface opposite to the top surface. The dummy substrate is exposed through the bottom surface of the mold layer.
-
公开(公告)号：US20210111128A1
公开(公告)日：2021-04-15
申请号：US17130505
申请日：2020-12-22
发明人： KYOUNG LIM SUK , Seung-Kwan Ryu , Seokhyun Lee
IPC分类号： H01L23/538 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/00 , H01L25/10 , H01L25/00
摘要： A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.
-
公开(公告)号：US10734367B2
公开(公告)日：2020-08-04
申请号：US16232159
申请日：2018-12-26
发明人： Seung-Kwan Ryu , Yonghwan Kwon , Yun Seok Choi , Chajea Jo , Taeje Cho
摘要： A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.
-
-
-
-
搜索结果
5 条记录 (耗时 0.046 秒)
