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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09035394B2

    公开(公告)日：2015-05-19

    申请号：US14146919

    申请日：2014-01-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seung-Uk Han ,  Nam-Ho Jeon

    IPC: H01L21/02 ,  H01L27/088 ,  H01L29/94 ,  H01L21/70 ,  H01L29/423 ,  H01L21/8234

    CPC classification number: H01L29/42376 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/4238 ,  H01L29/78

    Abstract: A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the active region over a channel between the first region and the second region and including at least one first gate tab protruding in a second direction toward the first region, and first and second contact plugs. The first gate tab covers and extends along a boundary between the active region and the device isolation layer. The first contact plug is disposed over the first region, the second contact plug is disposed over the second region, and the second contact plug has an effective width, as measured in the first direction, greater than that of the first contact plug.

    Abstract translation: 半导体器件包括由器件隔离层限定并包括第一和第二部分或区域的有源区域，在第一区域和第二区域之间的沟道上跨越有源区域沿第一方向延伸的栅电极，并且包括至少一个 第一栅极突片沿第二方向朝向第一区域突出，以及第一和第二接触插塞。 第一栅极突片覆盖并沿着有源区域和器件隔离层之间的边界延伸。 所述第一接触插塞设置在所述第一区域上，所述第二接触插塞设置在所述第二区域上，并且所述第二接触插塞具有在所述第一方向上测得的有效宽度大于所述第一接触插塞的有效宽度。

    Capacitorless memory device
    2.
    发明授权
    Capacitorless memory device 有权
    无电容存储器件

    公开(公告)号：US08941173B2

    公开(公告)日：2015-01-27

    申请号：US13775586

    申请日：2013-02-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-Uk Han ,  Jae-Hoon Lee ,  Jun-Su Kim ,  Satoru Yamada ,  Jin-Seong Lee ,  Nam-Ho Jeon

    IPC: H01L29/66 ,  H01L27/088 ,  H01L27/11 ,  H01L27/108

    CPC classification number: H01L27/088 ,  H01L27/108 ,  H01L27/11

    Abstract: According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.

    Abstract translation: 根据本发明构思的示例性实施例，一种无电容器存储器件包括：无电容器存储器单元，其在衬底上包括位线; 读取晶体管和写入晶体管。 读取晶体管可以包括在位线上沿垂直方向堆叠的第一至第三杂质层。 第一和第三层可以是第一导电类型，并且第二杂质层可以是不同于第一导电类型的第二导电类型。 写入晶体管可以包括在基板上沿垂直方向堆叠的源极层，主体层和漏极层，以及与主体层的侧表面相邻的栅极线。 栅极线可以与主体层的侧表面间隔开。 源极层可以与第二杂质层的侧表面相邻。

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