公开(公告)号：US12096147B2

公开(公告)日：2024-09-17

申请号：US17878285

申请日：2022-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Yong Kim ,  Kyung-Min Kim ,  Hyuk Oh ,  Hyeok Jong Lee ,  Seung Hoon Jung ,  Woong Joo ,  Hee Sung Chae

IPC: H04N25/75 ,  H04N25/709 ,  H03M1/56

CPC classification number: H04N25/75 ,  H04N25/709 ,  H03M1/56

Abstract: An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.

公开(公告)号：US11528440B2

公开(公告)日：2022-12-13

申请号：US17497558

申请日：2021-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Yong Kim ,  Myung Lae Chu ,  Min Woong Seo ,  Jun An Lee

IPC: H04N5/376 ,  H04N5/374 ,  H04N5/369 ,  H04N5/378 ,  H03M1/56 ,  H03M1/82 ,  H04N5/3745 ,  H04N5/365

Abstract: A digital pixel sensor for correcting and reducing a mismatch between a pixel and an analog digital converter provided. The digital pixel sensor includes a pixel array including a plurality of pixels; and a bank disposed on the pixel array. The bank includes: a plurality of comparators disposed on the plurality of pixels and configured to compare each of a plurality of pixel signals output from the plurality of pixels with a reference signal to output a plurality of comparison result signals; and a counter connected to the plurality of comparators, and configured to receive the plurality of comparison result signals and latch count code based on the plurality of comparison result signals.

公开(公告)号：US20220191419A1

公开(公告)日：2022-06-16

申请号：US17497558

申请日：2021-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Yong Kim ,  Myung Lae Chu ,  Min Woong Seo ,  Jun An Lee

IPC: H04N5/3745 ,  H04N5/376 ,  H04N5/365 ,  H03M1/56

Abstract: A digital pixel sensor for correcting and reducing a mismatch between a pixel and an analog digital converter provided. The digital pixel sensor includes a pixel array including a plurality of pixels; and a bank disposed on the pixel array. The bank includes: a plurality of comparators disposed on the plurality of pixels and configured to compare each of a plurality of pixel signals output from the plurality of pixels with a reference signal to output a plurality of comparison result signals; and a counter connected to the plurality of comparators, and configured to receive the plurality of comparison result signals and latch count code based on the plurality of comparison result signals.

公开(公告)号：US12238437B2

公开(公告)日：2025-02-25

申请号：US17895340

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Yong Kim ,  Jae Jin Jung

IPC: H04N25/75 ,  H04N25/63 ,  H04N25/71 ,  H04N25/772

Abstract: An image sensing device providing improved image quality includes a pixel array that outputs a pixel signal, a comparator that outputs a comparison result signal by comparing a reference signal and the pixel signal, a counter that outputs a count result signal having m bits by counting the comparison result signal, and an image signal processor that outputs an image signal having n bits by correcting the count result signal, wherein m and n are integers, and m is greater than n.

公开(公告)号：US11445139B2

公开(公告)日：2022-09-13

申请号：US16746213

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Yong Kim ,  Kyung-Min Kim ,  Hyuk Oh ,  Hyeok Jong Lee ,  Seung Hoon Jung ,  Woong Joo ,  Hee Sung Chae

IPC: H04N5/378 ,  H04N5/369 ,  H03M1/56

Abstract: An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.