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公开(公告)号：US12096147B2
公开(公告)日：2024-09-17
申请号：US17878285
申请日：2022-08-01
发明人： Sung Yong Kim , Kyung-Min Kim , Hyuk Oh , Hyeok Jong Lee , Seung Hoon Jung , Woong Joo , Hee Sung Chae
IPC分类号： H04N25/75 , H04N25/709 , H03M1/56
CPC分类号： H04N25/75 , H04N25/709 , H03M1/56
摘要： An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.
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公开(公告)号：US10666883B2
公开(公告)日：2020-05-26
申请号：US15940421
申请日：2018-03-29
发明人： Moo Young Kim , KyoungMin Koh , Woong Joo , Mira Lee , Kyung-Min Kim
摘要： An electronic circuit includes a unit pixel, a first clamp circuit, and a second clamp circuit. The unit pixel outputs a voltage having an output voltage level at a first output voltage level in a first time interval and at a second output voltage level in a second time interval different from the first time interval. The first clamp circuit is configured to clamp the output voltage level from the unit pixel to a first voltage level responsive to the first output voltage level being not greater than the first voltage level in the first time interval. The second clamp circuit is configured to clamp the output voltage level from the unit pixel to a second voltage level responsive to the second output voltage level being not greater than the second voltage level in the second time interval.
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公开(公告)号：US10389956B2
公开(公告)日：2019-08-20
申请号：US15873057
申请日：2018-01-17
发明人： Moo Young Kim , Kyoung Min Koh , Woong Joo , Mi Ra Lee
IPC分类号： H04N5/378 , H04N5/357 , H04N5/372 , H04N5/3745
摘要： Provided are image sensors. An image sensor includes a pixel array comprising pixels configured to output signal voltages, each of the pixels comprising first and second photodiodes, first and second transfer transistors connected to the first and second photodiodes, respectively, and a floating diffusion node to which the first and second transfer transistors are connected; a ramp voltage generator configured to generate a ramp voltage that decreases with a slope according to a ramp clock to have a first gain; a correlation double sampler (CDS) configured to compare the ramp voltage with the signal voltages to output a comparison signal; a counter configured to count the comparison signal according to a counter clock to output a digital signal; and a digital scaling unit configured to scale the digital signal to have a second gain.
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公开(公告)号：US11445139B2
公开(公告)日：2022-09-13
申请号：US16746213
申请日：2020-01-17
发明人： Sung Yong Kim , Kyung-Min Kim , Hyuk Oh , Hyeok Jong Lee , Seung Hoon Jung , Woong Joo , Hee Sung Chae
摘要： An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.
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公开(公告)号：US11019286B2
公开(公告)日：2021-05-25
申请号：US16439354
申请日：2019-06-12
发明人： Hee Sung Shim , Kyung Ha Kim , Mi Ra Lee , Woong Joo
IPC分类号： H04N5/341 , H04N5/353 , H04N5/378 , H01L27/146
摘要： A pixel driving circuit of an image sensor includes a first transistor to transmit an output signal of the photodiode to a floating diffusion node, a second transistor to reset a voltage of the floating diffusion node to a pixel voltage, a third transistor to output charges in the floating diffusion node, a fourth transistor to pre-charge an output node of the third transistor, a fifth transistor to transmit the charges in the floating diffusion node to a first node, a sixth transistor to transmit the pixel voltage to a second node, a seventh transistor to output charges in the second node, an eighth transistor to output an output signal of the seventh transistor to a column line, and a ninth transistor to output an output signal of the third transistor to the column line.
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公开(公告)号：US20200252560A1
公开(公告)日：2020-08-06
申请号：US16855075
申请日：2020-04-22
发明人： Moo Young Kim , KyoungMin Koh , Woong Joo , Mira Lee , Kyung-Min Kim
摘要： An electronic circuit includes a unit pixel, a first clamp circuit, and a second clamp circuit. The unit pixel outputs a voltage having an output voltage level at a first output voltage level in a first time interval and at a second output voltage level in a second time interval different from the first time interval. The first clamp circuit is configured to clamp the output voltage level from the unit pixel to a first voltage level responsive to the first output voltage level being not greater than the first voltage level in the first time interval. The second clamp circuit is configured to clamp the output voltage level from the unit pixel to a second voltage level responsive to the second output voltage level being not greater than the second voltage level in the second time interval.
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公开(公告)号：US20190007632A1
公开(公告)日：2019-01-03
申请号：US15940421
申请日：2018-03-29
发明人： Moo Young Kim , KyoungMin Koh , Woong Joo , Mira Lee , Kyung-Min Kim
CPC分类号： H04N5/359 , H01L27/14634 , H04N5/3577 , H04N5/3595 , H04N5/3698 , H04N5/374 , H04N5/378
摘要： An electronic circuit includes a unit pixel, a first clamp circuit, and a second clamp circuit. The unit pixel outputs a voltage having an output voltage level at a first output voltage level in a first time interval and at a second output voltage level in a second time interval different from the first time interval. The first clamp circuit is configured to clamp the output voltage level from the unit pixel to a first voltage level responsive to the first output voltage level being not greater than the first voltage level in the first time interval. The second clamp circuit is configured to clamp the output voltage level from the unit pixel to a second voltage level responsive to the second output voltage level being not greater than the second voltage level in the second time interval.
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公开(公告)号：US20180205897A1
公开(公告)日：2018-07-19
申请号：US15873057
申请日：2018-01-17
发明人： Moo Young KIM , Kyoung Min Koh , Woong Joo , Mi Ra Lee
CPC分类号： H04N5/3575 , H04N5/37213 , H04N5/37457 , H04N5/378
摘要： Provided are image sensors. An image sensor includes a pixel array comprising pixels configured to output signal voltages, each of the pixels comprising first and second photodiodes, first and second transfer transistors connected to the first and second photodiodes, respectively, and a floating diffusion node to which the first and second transfer transistors are connected; a ramp voltage generator configured to generate a ramp voltage that decreases with a slope according to a ramp clock to have a first gain; a correlation double sampler (CDS) configured to compare the ramp voltage with the signal voltages to output a comparison signal; a counter configured to count the comparison signal according to a counter clock to output a digital signal; and a digital scaling unit configured to scale the digital signal to have a second gain.
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公开(公告)号：US12063447B2
公开(公告)日：2024-08-13
申请号：US17973149
申请日：2022-10-25
发明人： Jaehoon Jun , Hyukbin Kwon , Woong Joo
IPC分类号： H04N25/75 , H04N25/709
CPC分类号： H04N25/75 , H04N25/709
摘要： Disclosed is a circuit which includes a first amplifier that generates a first output signal by comparing a first pixel signal corresponding to a first conversion gain and a first ramp signal and generates a second output signal by comparing a second pixel signal corresponding to a second conversion gain and a second ramp signal, and a second amplifier that generates a third output signal based on the first output signal and generates a fourth output signal based on the second output signal, the first conversion gain is higher than the second conversion gain, and a first power current of the first amplifier when the first pixel signal and the first ramp signal are compared is different from a second power current of the first amplifier when the second pixel signal and the second ramp signal are compared.
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公开(公告)号：US11418736B2
公开(公告)日：2022-08-16
申请号：US16855075
申请日：2020-04-22
发明人： Moo Young Kim , KyoungMin Koh , Woong Joo , Mira Lee , Kyung-Min Kim
摘要： An electronic circuit includes a unit pixel, a first clamp circuit, and a second clamp circuit. The unit pixel outputs a voltage having an output voltage level at a first output voltage level in a first time interval and at a second output voltage level in a second time interval different from the first time interval. The first clamp circuit is configured to clamp the output voltage level from the unit pixel to a first voltage level responsive to the first output voltage level being not greater than the first voltage level in the first time interval. The second clamp circuit is configured to clamp the output voltage level from the unit pixel to a second voltage level responsive to the second output voltage level being not greater than the second voltage level in the second time interval.
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