Memory device with improved program performance and method of operating the same

    公开(公告)号:US11600331B2

    公开(公告)日:2023-03-07

    申请号:US17524099

    申请日:2021-11-11

    Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

    Nonvolatile memory device including a verify circuit to control word and bit line voltages and method of operating the same

    公开(公告)号:US11605432B2

    公开(公告)日:2023-03-14

    申请号:US17552116

    申请日:2021-12-15

    Inventor: Sung-Min Joe

    Abstract: According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.

    Nonvolatile memory device including a logic circuit to control word line voltages

    公开(公告)号:US12159675B2

    公开(公告)日:2024-12-03

    申请号:US18522829

    申请日:2023-11-29

    Inventor: Sung-Min Joe

    Abstract: According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.

    Memory device with improved program performance and method of operating the same

    公开(公告)号:US11152074B2

    公开(公告)日:2021-10-19

    申请号:US16998273

    申请日:2020-08-20

    Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and connected to the memory cell region by the first and second metal pads, and a memory cell array in the memory cell region and including cell strings. The cell strings include memory cells, word lines and dummy lines connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings. The memory device further includes control logic in the peripheral circuit region and including a precharge control circuit that controls a precharge on partial cell strings among the cell strings and controls data program steps on the memory cells, and a row decoder in the peripheral circuit region that activates at least some of the word lines based on control of the control logic.

    NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME

    公开(公告)号:US20230215499A1

    公开(公告)日:2023-07-06

    申请号:US18175043

    申请日:2023-02-27

    Inventor: Sung-Min Joe

    Abstract: According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.

    Memory device with improved program performance and method of operating the same

    公开(公告)号:US11217311B2

    公开(公告)日:2022-01-04

    申请号:US16927100

    申请日:2020-07-13

    Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

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