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公开(公告)号：US11348627B2
公开(公告)日：2022-05-31
申请号：US17127732
申请日：2020-12-18
发明人： Dmytro Apalkov , Sungchul Lee , Roman Chepulskyy
摘要： A system including a racetrack memory layer is described. The racetrack memory layer includes a plurality of bit locations and a plurality of domain wall traps. The bit locations are interleaved with the domain wall traps. Each of the bit locations has a first domain wall speed. Each of the domain wall traps has a second domain wall speed. The first domain wall speed is greater than the second domain wall speed. The first domain wall speed and the second domain wall speed are due to at least one of a Dzyaloshinskii-Moriya interaction variation in the racetrack memory layer, a synthetic antiferromagnetic effect variation in the racetrack memory layer, and a separation distance for the plurality of domain wall traps corresponding to an intrinsic travel distance. The separation distance is less than one hundred nanometers.
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公开(公告)号：US20220068338A1
公开(公告)日：2022-03-03
申请号：US17127732
申请日：2020-12-18
发明人： Dmytro Apalkov , Sungchul Lee , Roman Chepulskyy
摘要： A system including a racetrack memory layer is described. The racetrack memory layer includes a plurality of bit locations and a plurality of domain wall traps. The bit locations are interleaved with the domain wall traps. Each of the bit locations has a first domain wall speed. Each of the domain wall traps has a second domain wall speed. The first domain wall speed is greater than the second domain wall speed. The first domain wall speed and the second domain wall speed are due to at least one of a Dzyaloshinskii-Moriya interaction variation in the racetrack memory layer, a synthetic antiferromagnetic effect variation in the racetrack memory layer, and a separation distance for the plurality of domain wall traps corresponding to an intrinsic travel distance. The separation distance is less than one hundred nanometers.
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公开(公告)号：US12112784B2
公开(公告)日：2024-10-08
申请号：US17751898
申请日：2022-05-24
发明人： Sungchul Lee , Kyungjin Lee
CPC分类号： G11C11/161 , H10B61/00 , H10N50/10 , H10N50/80 , H10N50/85
摘要： A magneto resistive random access memory (MRAM) device including a spin orbit torque structure including a stack of an oxide layer pattern, a ferromagnetic pattern, and a non-magnetic pattern; and a magnetic tunnel junction (MTJ) structure on the spin orbit torque structure, the MTJ structure including a stack of a free layer pattern, a tunnel barrier pattern, and a pinned layer pattern, wherein the spin orbit torque structure extends in a first direction parallel to an upper surface of the spin orbit torque structure, the ferromagnetic pattern includes a horizontal magnetic material, and the free layer pattern has a magnetization direction in a vertical direction perpendicular to the upper surface of the spin orbit torque structure, the magnetization direction being changeable in response to spin currents generated in the spin orbit torque structure.
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公开(公告)号：US11227665B2
公开(公告)日：2022-01-18
申请号：US17001740
申请日：2020-08-25
发明人： Eunsun Noh , Sungchul Lee , Unghwan Pi
摘要： A magnetic memory device includes a reading unit on a substrate, a magnetic track layer on the reading unit, the magnetic track layer including a bottom portion between first and second sidewall portions, and a mold structure on the bottom portion of the magnetic track layer, and between the first and second sidewall portions. The mold structure includes first and second mold layers alternately arranged in a first direction perpendicular to a top surface of the substrate, and the magnetic track layer includes magnetic domains and magnetic domain walls between magnetic domains, the first and second sidewall portions of the magnetic track layer including sidewall notches corresponding to the magnetic domain walls, and the bottom portion includes a bottom notch corresponding to one of the magnetic domain walls.
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