公开(公告)号：US12009328B2

公开(公告)日：2024-06-11

申请号：US17715479

申请日：2022-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Taewon Yoo ,  Myungkee Chung

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05551

Abstract: A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.

公开(公告)号：US20220285328A1

公开(公告)日：2022-09-08

申请号：US17648424

申请日：2022-01-20

Applicant: Samsung Electronics Co., LTD

Inventor： DONGKYU KIM ,  Daeho Lee ,  Seokhyun Lee ,  Minjung Kim ,  Taewon Yoo

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a lower semiconductor chip disposed on a lower redistribution substrate, lower solder patterns disposed between the lower redistribution substrate and the lower semiconductor chip, conductive structures disposed on the lower redistribution substrate, a lower molding layer disposed on the lower redistribution substrate and covering a top surface of the lower semiconductor chip, an upper redistribution substrate disposed on the lower molding layer and electrically connected to the conductive structures, an upper semiconductor chip disposed on the upper redistribution substrate, upper solder patterns disposed between the upper redistribution substrate and the upper semiconductor chip, and an upper molding layer disposed on the upper redistribution substrate and covering a sidewall of the upper semiconductor chip. The number of the conductive structures is greater than that of chip pads of the upper semiconductor chip.

公开(公告)号：US11362054B2

公开(公告)日：2022-06-14

申请号：US16923428

申请日：2020-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Taewon Yoo ,  Myungkee Chung

IPC: H01L23/00

Abstract: A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.

公开(公告)号：US11164805B2

公开(公告)日：2021-11-02

申请号：US16814455

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong Kim ,  Taewon Yoo

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

公开(公告)号：US11705418B2

公开(公告)日：2023-07-18

申请号：US17018259

申请日：2020-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Taewon Yoo ,  Myungkee Chung

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L23/31 ,  H01L23/53238 ,  H01L23/562

Abstract: A semiconductor package includes a semiconductor chip including a contact pad on an active surface, a first insulating layer on the active surface including a first opening that exposes the contact pad, a redistribution layer connected to the contact pad and extending to an upper surface of the first insulating layer, a second insulating layer on the first insulating layer and including a second opening that exposes a contact region of the redistribution layer, a conductive post on the contact region, an encapsulation layer on the second insulating layer and surrounding the conductive post, and a conductive bump on an upper surface of the conductive post. The conductive post includes an intermetallic compound (IMC) layer in contact with the conductive bump. An upper surface of the IMC layer is lower than an upper surface of the encapsulation layer.

公开(公告)号：US11676875B2

公开(公告)日：2023-06-13

申请号：US17488662

申请日：2021-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong Kim ,  Taewon Yoo

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L23/29 ,  H01L23/3114 ,  H01L24/13

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

公开(公告)号：US20220375829A1

公开(公告)日：2022-11-24

申请号：US17533606

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Minjung Kim ,  Dongkyu Kim ,  Taewon Yoo

IPC: H01L23/49 ,  H01L23/498 ,  H01L23/31

Abstract: Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.

公开(公告)号：US11296004B2

公开(公告)日：2022-04-05

申请号：US16710841

申请日：2019-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewon Yoo ,  Hyunsoo Chung ,  Myungkee Chung

IPC: H01L23/36 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is provided including a first semiconductor package including a first semiconductor chip. The first semiconductor chip includes a first surface and a second surface opposite to the first surface. A second semiconductor package is disposed on the first semiconductor package. The second semiconductor package includes a second redistribution layer including a redistribution line. A second semiconductor chip is disposed on the second redistribution layer. A thermal pillar is disposed on the second redistribution layer. A heat radiator is disposed on the second semiconductor package and connected to the thermal pillar. The redistribution line is connected to the first semiconductor chip.

公开(公告)号：US12191236B2

公开(公告)日：2025-01-07

申请号：US17533606

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Minjung Kim ,  Dongkyu Kim ,  Taewon Yoo

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/49 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.

公开(公告)号：US12154889B2

公开(公告)日：2024-11-26

申请号：US17370594

申请日：2021-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Taewon Yoo ,  Myungkee Chung ,  Jinchan Ahn

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip and a redistribution layer. The semiconductor chip includes a semiconductor substrate, a passivation layer, and first power, second power, and signal pads exposed from the passivation layer. The redistribution layer includes a photosensitive dielectric layer, and first to third redistribution patterns and a high-k dielectric pattern that are in the photosensitive dielectric layer. The first, second, and third redistribution patterns are respectively connected to the first power, second power, and signal pads. The high-k dielectric pattern is between the first and second redistribution patterns. The photosensitive dielectric layer includes a first dielectric material. The high-k dielectric pattern includes a second dielectric material whose dielectric constant greater than that of the first dielectric material. The high-k dielectric pattern is in contact with the passivation layer. The passivation layer includes a dielectric material different from the first and second dielectric materials.