公开(公告)号：US09184178B2

公开(公告)日：2015-11-10

申请号：US14564364

申请日：2014-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract translation: 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。

公开(公告)号：US09178039B2

公开(公告)日：2015-11-03

申请号：US14052072

申请日：2013-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwa Park ,  Woong-Hee Sohn ,  Man-Sug Kang ,  Hee-Sook Park

IPC: H01L29/66 ,  H01L27/108

CPC classification number: H01L29/66621 ,  H01L27/10876

Abstract: A semiconductor device includes a gate trench across an active region of a semiconductor substrate, a gate structure filling the gate trench, and source/drain regions formed in the active region at respective sides of the gate structure. The gate structure includes a sequentially stacked gate electrode and insulating capping pattern, and a gate dielectric layer between the gate electrode and the active region. The gate electrode is located at a lower level than an upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first part having a first width and a second part having a second width greater than the first width. The barrier conductive pattern is interposed between the first part of the gate conductive pattern and the gate dielectric layer.

Abstract translation: 半导体器件包括跨越半导体衬底的有源区的栅极沟槽，填充栅极沟槽的栅极结构以及形成在栅极结构的相应侧的有源区中的源极/漏极区。 栅极结构包括顺序层叠的栅极电极和绝缘覆盖图案，以及栅电极和有源区之间的栅介质层。 栅电极位于比有源区的上表面更低的电平，并且包括阻挡导电图案和栅极导电图案。 栅极导电图案包括具有第一宽度的第一部分和具有大于第一宽度的第二宽度的第二部分。 阻挡导电图案插入在栅极导电图案的第一部分和栅极电介质层之间。

公开(公告)号：US20150091078A1

公开(公告)日：2015-04-02

申请号：US14564364

申请日：2014-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract translation: 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。