公开(公告)号：US09184178B2

公开(公告)日：2015-11-10

申请号：US14564364

申请日：2014-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract translation: 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。

公开(公告)号：US09299826B2

公开(公告)日：2016-03-29

申请号：US14204441

申请日：2014-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Il-Woo Kim ,  Jeong-Gil Lee ,  Yong-Il Kwon ,  Myoung-Bum Lee

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L29/78 ,  H01L21/76805 ,  H01L21/76831 ,  H01L27/11529 ,  H01L29/66825

Abstract: A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.

Abstract translation: 存储器件包括栅极结构，接触插塞和间隔物。 栅极结构包括顺序地堆叠在衬底上的第一和第二导电层图案。 接触插塞穿过第二导电层图案，并且接触插塞的侧壁直接接触第二导电层图案的至少一部分。 间隔件围绕接触塞的侧壁的一部分并接触门结构。

公开(公告)号：US20150091078A1

公开(公告)日：2015-04-02

申请号：US14564364

申请日：2014-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract translation: 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。