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公开(公告)号：US10693503B2
公开(公告)日：2020-06-23
申请号：US16013053
申请日：2018-06-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Min Shin , Min Uk Kim , Ki Jun Lee , Jun Jin Kong , Hong Rak Son
Abstract: A polar code encoding and decoding method includes generating a first and second sub-codewords. The sub-codewords correspond to pre-codewords, and the pre-codewords have a shared data aspect. The sub-codewords provide useful error-recovery for data stored in a memory. When data is read from the memory, decoding takes place. The data read operation may include hard decision decoding, soft decision decoding, or hard decision decoding followed by soft decision decoding. In the method, the shared data aspect is used to decode a first sub-codeword for which decoding was not initially successful. An apparatus is also provided.
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公开(公告)号：US11200117B2
公开(公告)日：2021-12-14
申请号：US17029912
申请日：2020-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myung Kyu Lee , Jun Jin Kong , Ki Jun Lee , Sung Hye Cho , Dae Hyun Kim , Yong Gyu Chu
Abstract: Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.
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公开(公告)号：US10324785B2
公开(公告)日：2019-06-18
申请号：US15652521
申请日：2017-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Rae Kim , Gyu Yeol Kong , Ki Jun Lee , Jun Jin Kong , Hong Rak Son , Beom Kyu Shin , Heon Hwa Cheong
Abstract: A decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes.
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Patent Agency Ranking
公开(公告)号：US10824507B2
公开(公告)日：2020-11-03
申请号：US16372047
申请日：2019-04-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myung Kyu Lee , Jun Jin Kong , Ki Jun Lee , Sung Hye Cho , Dae Hyun Kim , Yong Gyu Chu
Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.
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公开(公告)号：US20180024879A1
公开(公告)日：2018-01-25
申请号：US15652521
申请日：2017-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Rae KIM , Gyu Yeol Kong , Ki Jun Lee , Jun Jin Kong , Hong Rak Son , Beom Kyu Shin , Heon Hwa Cheong
CPC classification number: G06F11/1068 , G06F11/1012 , G11C29/52 , H03M13/1111 , H03M13/3723 , H03M13/6325
Abstract: A decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes.
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公开(公告)号：US20250078947A1
公开(公告)日：2025-03-06
申请号：US18949589
申请日：2024-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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公开(公告)号：US12205661B2
公开(公告)日：2025-01-21
申请号：US18093560
申请日：2023-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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公开(公告)号：US11551776B2
公开(公告)日：2023-01-10
申请号：US17392382
申请日：2021-08-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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