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公开(公告)号：US10824507B2
公开(公告)日：2020-11-03
申请号：US16372047
申请日：2019-04-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myung Kyu Lee , Jun Jin Kong , Ki Jun Lee , Sung Hye Cho , Dae Hyun Kim , Yong Gyu Chu
Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.
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公开(公告)号：US11200117B2
公开(公告)日：2021-12-14
申请号：US17029912
申请日：2020-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myung Kyu Lee , Jun Jin Kong , Ki Jun Lee , Sung Hye Cho , Dae Hyun Kim , Yong Gyu Chu
Abstract: Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.
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Patent Agency Ranking
公开(公告)号：US20180088856A1
公开(公告)日：2018-03-29
申请号：US15696443
申请日：2017-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Geun Yeong YU , Beom Kyu Shin , Myung Kyu Lee , Jun Jin Kong , Hong Rak Son
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/0604 , G06F3/0614 , G06F3/0647 , G06F3/0688 , G06F3/0689
Abstract: A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.
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公开(公告)号：US11016689B2
公开(公告)日：2021-05-25
申请号：US15696443
申请日：2017-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Geun Yeong Yu , Beom Kyu Shin , Myung Kyu Lee , Jun Jin Kong , Hong Rak Son
IPC: G06F3/06
Abstract: A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.
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公开(公告)号：US20250078947A1
公开(公告)日：2025-03-06
申请号：US18949589
申请日：2024-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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公开(公告)号：US12205661B2
公开(公告)日：2025-01-21
申请号：US18093560
申请日：2023-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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公开(公告)号：US11551776B2
公开(公告)日：2023-01-10
申请号：US17392382
申请日：2021-08-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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