公开(公告)号：US11075193B2

公开(公告)日：2021-07-27

申请号：US16418885

申请日：2019-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Sam Kang ,  Young Gwan Ko ,  Yong Jin Park ,  Seon Hee Moon

IPC: H01L23/552 ,  H01L25/16 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a frame disposed on the connection structure and having a through-hole, a semiconductor chip disposed in the through-hole on the connection structure and having a connection pad disposed to face the connection structure, and a passive component disposed on the frame.

公开(公告)号：US10825775B2

公开(公告)日：2020-11-03

申请号：US16149102

申请日：2018-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Sam Kang ,  Jin Su Kim ,  Yong Jin Park ,  Young Gwan Ko ,  Yong Jin Seol

IPC: H01L29/00 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a support member including a resin body having a first surface and a second surface opposing each other and having a cavity, and at least one passive component embedded in the resin body and having a connection terminal exposed from the first surface; a first connection member disposed on the first surface of the resin body, and having a first redistribution layer on the first insulating layer and connected to the connection terminal; a second connection member disposed on the first connection member and covering the cavity, and having a second redistribution layer on the second insulating layer and connected to the first redistribution layer; and a semiconductor chip disposed on the second connection member in the cavity.

公开(公告)号：US10818604B2

公开(公告)日：2020-10-27

申请号：US16414016

申请日：2019-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Sam Kang ,  Yong Jin Park ,  Young Gwan Ko ,  Moon Il Kim

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip having connection pads on one surface thereof, a first encapsulant covering at least portions of the semiconductor chip, and a connection structure disposed on the one surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pads. A wiring structure is disposed on one surface of the first encapsulant opposing another surface of the first encapsulant facing towards the connection structure. The wiring structure has a passive component embedded therein, and includes one or more wiring layers electrically connected to the passive component. The one or more redistribution layers and the one or more wiring layers are electrically connected to each other.

公开(公告)号：US20250022799A1

公开(公告)日：2025-01-16

申请号：US18748488

申请日：2024-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Jin Park ,  Ji Hwan Hwang

IPC: H01L23/528 ,  H01L21/3105 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

Abstract: Semiconductor package and fabricating method thereof are provided. Semiconductor package comprises a buffer die including a semiconductor substrate having a first surface and a second surface, which face each other, and a passivation layer formed on the first surface, a plurality of core chips stacked on the buffer die, including a first core chip, which is disposed at a lowermost end, among the plurality of core chips, an adhesive layer between the buffer die and the first core chip, and a mold layer surrounding an upper surface of the buffer die and the plurality of core chips, wherein a plurality of recesses recessed inward from an upper surface of the passivation layer are formed on the upper surface of the passivation layer, and the plurality of recesses are formed to surround the first core chip and do not overlap the first core chip horizontally.

公开(公告)号：US11048364B2

公开(公告)日：2021-06-29

申请号：US16549714

申请日：2019-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Jin Park ,  Min Gyu Kim ,  Sun Kwon Kim ,  Jong Bin Moon ,  Young Kil Choi ,  Yoon Kyung Choi

IPC: G06F3/044 ,  G01R27/26

Abstract: A method for acquiring capacitance of a capacitive touch panel includes acquiring a selected capacitance value at a selected point among a plurality of points at which a plurality of capacitances are present, in the capacitive touch panel, determining the selected capacitance value as a reference capacitance value, and performing a multi-driving using a balanced code, and acquiring a capacitance value from at least one point among the plurality of points using the reference capacitance value.