公开(公告)号：US20200185815A1

公开(公告)日：2020-06-11

申请号：US16410853

申请日：2019-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Koon Lee ,  Jin Su Kim

IPC: H01Q1/22 ,  H01Q9/16 ,  H01Q1/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: An antenna module includes an antenna substrate having a first surface and a second surface disposed to oppose each other, and including a substrate wiring layer having a first antenna pattern positioned in a first region, a second antenna pattern disposed in a second region adjacent to one side, and first and second feed patterns connected to the first and second antenna patterns, respectively; and a semiconductor package including a connection structure disposed on the second surface except for an area overlapping with the second region of the antenna substrate and redistribution layers electrically connected to the substrate wiring layer, and at least one semiconductor chip having connection pads connected to the redistribution layers. A region overlapping with the second feed pattern in each of the plurality of redistribution layers is provided as an opened region.

公开(公告)号：US10345698B2

公开(公告)日：2019-07-09

申请号：US15606170

申请日：2017-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Beom Yoo ,  Sung Won Kwon ,  Dong Wook Shin ,  Mun Ja Kim ,  Jin Su Kim ,  Hwan Chul Jeon

IPC: G03F1/62 ,  G03F1/80 ,  H01L21/027 ,  G03F1/22 ,  G03F7/20

Abstract: A method for fabricating a semiconductor device includes forming a pellicle including an amorphous carbon layer, attaching the pellicle onto a reticle, and forming a photoresist pattern by utilizing EUV light transmitted through the pellicle and reflected by the reticle. The forming the pellicle includes forming a first dielectric layer on a first side of the substrate, forming the amorphous carbon layer on the first dielectric layer, forming a second dielectric layer on a second side of the substrate opposite to the first side of the substrate, etching the second dielectric layer overlapping the first region of the substrate to form a mask pattern, and forming a support including the second region of the substrate and the remaining part of the first dielectric layer. The forming the support includes etching the first region of the substrate and the first dielectric layer on the first region.

公开(公告)号：US11923314B2

公开(公告)日：2024-03-05

申请号：US17203312

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ik Kyu Jin ,  Jin Su Kim ,  Ki Ju Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19106

Abstract: A semiconductor package includes a connection structure including a redistribution layer, a plurality of under bump metal layers electrically connected to the redistribution layer, a passivation layer which overlaps at least portions of side faces of the plurality of under bump metal layers, and includes a first trench disposed between under bump metal layers adjacent to each other, a surface mounting element which is on the under bump metal layers adjacent to each other, connected to the redistribution layer, and overlaps the first trench, and an underfill material layer that is between a portion of the passivation layer and the surface mounting element, and is in the first trench. The first trench extends in a first direction and includes a first sub-trench having a first width in a second direction, and a second sub-trench having a second width different from the first width in the second direction.

公开(公告)号：US10825775B2

公开(公告)日：2020-11-03

申请号：US16149102

申请日：2018-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Sam Kang ,  Jin Su Kim ,  Yong Jin Park ,  Young Gwan Ko ,  Yong Jin Seol

IPC: H01L29/00 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a support member including a resin body having a first surface and a second surface opposing each other and having a cavity, and at least one passive component embedded in the resin body and having a connection terminal exposed from the first surface; a first connection member disposed on the first surface of the resin body, and having a first redistribution layer on the first insulating layer and connected to the connection terminal; a second connection member disposed on the first connection member and covering the cavity, and having a second redistribution layer on the second insulating layer and connected to the first redistribution layer; and a semiconductor chip disposed on the second connection member in the cavity.

公开(公告)号：US10522497B2

公开(公告)日：2019-12-31

申请号：US15988647

申请日：2018-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong Ho Lee ,  Bong Ju Cho ,  Young Gwan Ko ,  Jin Su Kim ,  Shang Hoon Seo ,  Jeong Il Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L21/683

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.

公开(公告)号：US10475748B2

公开(公告)日：2019-11-12

申请号：US15981651

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong Ho Lee ,  Myung Sam Kang ,  Young Gwan Ko ,  Shang Hoon Seo ,  Jin Su Kim

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; an electronic component disposed on the other surface of the frame opposing one surface of the frame in which the semiconductor chip is disposed; a second encapsulant covering at least portions of the electronic component; and a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer, wherein the connection pads and the electronic component are electrically connected to each other through the wiring layers and the redistribution layer.

公开(公告)号：US10410961B2

公开(公告)日：2019-09-10

申请号：US15978727

申请日：2018-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong Ho Lee ,  Myung Sam Kang ,  Young Gwan Ko ,  Jin Su Kim ,  Shang Hoon Seo ,  Jeong Il Lee

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other. The active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.

公开(公告)号：US10756021B2

公开(公告)日：2020-08-25

申请号：US15972820

申请日：2018-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Ju Lee ,  Jin Su Kim

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes: a connection member having first and second surfaces opposing each other and including a redistribution layer; a support member disposed on the first surface of the connection member, including a cavity, and having an inner sidewall surrounding the cavity of which an upper region is chamfered; a semiconductor chip disposed on the connection member in the cavity and having connection pads electrically connected to the redistribution layer; at least one electronic component disposed between the semiconductor chip and the inner sidewall and having connection terminals electrically connected to the redistribution layer; and an encapsulant encapsulating the semiconductor chip and the at least one electronic component disposed in the cavity.

公开(公告)号：US10475776B2

公开(公告)日：2019-11-12

申请号：US15900568

申请日：2018-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeong A Kim ,  Eun Sil Kim ,  Young Gwan Ko ,  Akihisa Kuroyanagi ,  Jin Su Kim ,  Jun Woo Myung

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/52 ,  H01L49/02 ,  H01L21/56 ,  H01L21/48

Abstract: A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.

公开(公告)号：US10727212B2

公开(公告)日：2020-07-28

申请号：US16170469

申请日：2018-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seon Hee Moon ,  Myung Sam Kang ,  Young Gwan Ko ,  Chang Bae Lee ,  Jin Su Kim

IPC: H01L23/498 ,  H01L25/16 ,  H01L23/053 ,  H01L23/31 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.