公开(公告)号：US20240030287A1

公开(公告)日：2024-01-25

申请号：US18340440

申请日：2023-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choeun LEE ,  Kyungho KIM ,  Kanghun MOON ,  Kihwan KIM ,  Yonguk JEON

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66439

Abstract: A semiconductor device includes a plurality of channel layers on an active region on a substrate, a gate structure surrounding each of the plurality of channel layers, and a source/drain region contacting the plurality of channel layers. The source/drain region comprises a first epitaxial layer including first layers, disposed on side surfaces of the plurality of channel layers, and a second layer, disposed at a lower end of the source/drain region on the active region, and having first impurities, a second epitaxial layer on the active region, filling a space between the first layers and the second layer, having second impurities, different from the first impurities, and having a recessed upper surface, and a third epitaxial layer on the second epitaxial layer. At least a portion of the third epitaxial layer may not include the first impurities and the second impurities.

公开(公告)号：US20230395660A1

公开(公告)日：2023-12-07

申请号：US18100688

申请日：2023-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihwan KIM ,  Kyungho KIM ,  Kanghun MOON ,  Choeun LEE ,  Yonguk JEON

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/775

Abstract: A semiconductor device, including a fin active region; a device isolation layer covering two sidewalls of the fin active region on the substrate; a gate structure; a nano-sheet structure including a plurality of nano-sheets; and source/drain regions disposed on the fin active region and adjacent to the gate structure, wherein each source/drain region of the source/drain regions includes a buffer layer, an inner impurity layer, and a central impurity layer which are sequentially stacked, wherein the buffer layer fills a first indentation between two vertically-adjacent nano-sheets and a second indentation between the top surface of the fin active region and a nano-sheet, and wherein the plurality of nano-sheets contact side surfaces of the inner impurity layer.

公开(公告)号：US20230387205A1

公开(公告)日：2023-11-30

申请号：US18100233

申请日：2023-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Hwan KIM ,  KYUNGHO KIM ,  KANG HUN MOON ,  CHOEUN LEE ,  Yonguk JEON

IPC: H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/6656

Abstract: A semiconductor device includes a substrate including an active pattern; a source/drain pattern on the active pattern; a gate electrode on the active pattern; and a gate spacer on the source/drain pattern. The source/drain pattern includes a first semiconductor layer on the active pattern and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes a first inner sidewall and second inner sidewall on the second semiconductor layer. A distance between the first and second inner sidewalls of the first semiconductor layer decreases according as positions of two portions of the first semiconductor layer where the distance is measured become closer to the gate spacer decreases.