公开(公告)号：US20220190112A1

公开(公告)日：2022-06-16

申请号：US17686700

申请日：2022-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Hee CHOI ,  Seokhoon KIM ,  Choeun LEE ,  Edward Namkyu CHO ,  Seung Hun LEE

IPC: H01L29/08 ,  H01L27/11 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/108

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.

公开(公告)号：US20230326970A1

公开(公告)日：2023-10-12

申请号：US18050684

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu CHO ,  Seokhoon KIM ,  Jeongho YOO ,  Choeun LEE ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/08 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L29/78696 ,  H01L27/092 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/41783 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673

Abstract: A semiconductor device includes a substrate including a first active pattern, a first channel pattern on the first active pattern, the first channel pattern including first, second, and third semiconductor patterns spaced apart from one another and vertically stacked, a first source/drain pattern connected to the first to third semiconductor patterns, and a gate electrode on the first to third semiconductor patterns. The first source/drain pattern includes a first protrusion protruding toward the first semiconductor pattern, a second protrusion protruding toward the second semiconductor pattern, and a third protrusion protruding toward the third semiconductor pattern. A width of the second protrusion is greater than a width of the first protrusion. A width of the third protrusion is greater than the width of the second protrusion.

公开(公告)号：US20180151705A1

公开(公告)日：2018-05-31

申请号：US15871479

申请日：2018-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Sujin JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

公开(公告)号：US20200020773A1

公开(公告)日：2020-01-16

申请号：US16452668

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Hee CHOI ,  Seokhoon KIM ,  Choeun LEE ,  Edward Namkyu CHO ,  Seung Hun LEE

IPC: H01L29/08 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.

公开(公告)号：US20180108779A1

公开(公告)日：2018-04-19

申请号：US15844863

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin JUNG ,  JinBum KIM ,  KANG HUN MOON ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Choeun LEE ,  Yang XU

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

公开(公告)号：US20160351715A1

公开(公告)日：2016-12-01

申请号：US15135566

申请日：2016-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin JUNG ,  JinBum KIM ,  KANG HUN MOON ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Choeun LEE ,  Yang XU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

Abstract translation: 公开了一种半导体器件。 该器件包括：衬底，其包括由器件隔离层限定的有源区，从衬底突出并沿第一方向延伸的鳍状图案，所述鳍图案包括栅极鳍区和源极/漏极鳍区，栅极图案设置 在所述栅极鳍区域上沿与所述第一方向交叉的第二方向延伸，以及设置在所述源极/漏极鳍片区域的侧壁上的源极/漏极部分。 当在第二方向上测量时，源极/漏极鳍片区域的宽度不同于栅极鳍片区域的第二方向上的宽度。

公开(公告)号：US20160359021A1

公开(公告)日：2016-12-08

申请号：US15134556

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Sujin JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

Abstract translation: 提供了形成集成电路器件的方法。 所述方法可以包括在衬底上形成栅极结构，在栅极结构的侧壁上形成第一蚀刻掩模，使用栅极结构和第一蚀刻掩模各向异性蚀刻衬底作为蚀刻掩模，以在衬底中形成预备凹槽 在所述初步凹槽中形成牺牲层，在所述第一蚀刻掩模上形成第二蚀刻掩模，使用所述栅极结构和所述第一和第二蚀刻掩模作为蚀刻掩模蚀刻所述牺牲层和所述牺牲层下方的所述衬底，以形成 源极/漏极凹部，并且在源极/漏极凹部中形成源极/漏极。 源极/漏极凹部的侧壁可以相对于第二蚀刻掩模的外表面朝向栅极结构凹陷。

公开(公告)号：US20150206956A1

公开(公告)日：2015-07-23

申请号：US14499922

申请日：2014-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  JUNGHO YOO ,  BYEONGCHAN LEE ,  Choeun LEE ,  HYUN JUNG LEE ,  Seong Hoon JEONG ,  BONYOUNG KOO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法包括形成从半导体衬底突出的有源图案，形成与有源图案交叉的伪栅极图案，在伪栅极图案的相对的第一和第二侧壁上形成栅极间隔物，将伪栅极图案去除 形成栅极区域，暴露栅极间隔件之间的有源图案的上表面和侧壁，凹陷由栅极区域暴露的有源图案的上表面，以形成通道凹槽区域，在通道凹槽区域中形成通道图案 选择性外延生长（SEG）工艺，以及顺序地形成覆盖栅极区域中的沟道图案的上表面和侧壁的栅极电介质层和栅电极。 沟道图案具有与半导体衬底不同的晶格常数。

公开(公告)号：US20150206955A1

公开(公告)日：2015-07-23

申请号：US14498996

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Seong Hoon JEONG ,  JEON IL LEE ,  SEOKHOON KIM ,  KWAN HEUM LEE ,  Choeun LEE ,  Yu-Jin PYO

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.

Abstract translation: 本发明构思提供制造半导体器件的方法。 该方法包括图案化衬底以形成有源图案，形成与有源图案相交的栅极图案，在栅极图案的侧壁上形成栅极间隔物，形成覆盖栅极图案的上部区域的生长抑制层，以及形成 源极/漏极在栅极图案的相对的第一和第二侧。

公开(公告)号：US20240030287A1

公开(公告)日：2024-01-25

申请号：US18340440

申请日：2023-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choeun LEE ,  Kyungho KIM ,  Kanghun MOON ,  Kihwan KIM ,  Yonguk JEON

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66439

Abstract: A semiconductor device includes a plurality of channel layers on an active region on a substrate, a gate structure surrounding each of the plurality of channel layers, and a source/drain region contacting the plurality of channel layers. The source/drain region comprises a first epitaxial layer including first layers, disposed on side surfaces of the plurality of channel layers, and a second layer, disposed at a lower end of the source/drain region on the active region, and having first impurities, a second epitaxial layer on the active region, filling a space between the first layers and the second layer, having second impurities, different from the first impurities, and having a recessed upper surface, and a third epitaxial layer on the second epitaxial layer. At least a portion of the third epitaxial layer may not include the first impurities and the second impurities.