公开(公告)号：US20210005663A1

公开(公告)日：2021-01-07

申请号：US17027980

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsu SON ,  Seung Pil KO ,  Jung Hyuk LEE ,  Shinhee HAN ,  Gwan-Hyeob KOH ,  Yoonjong SONG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

公开(公告)号：US20180309052A1

公开(公告)日：2018-10-25

申请号：US16018700

申请日：2018-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhee HAN ,  Kiseok SUH ,  KyungTae NAM ,  Woojin KIM ,  Kwangil SHIN ,  Minkyoung JOO ,  Gwanhyeob KOH

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.

公开(公告)号：US20190326355A1

公开(公告)日：2019-10-24

申请号：US16161370

申请日：2018-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsu SON ,  Seung Pil KO ,  Jung Hyuk LEE ,  Shinhee HAN ,  Gwan-Hyeob KOH ,  Yoonjong SONG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.