公开(公告)号：US20210005663A1

公开(公告)日：2021-01-07

申请号：US17027980

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsu SON ,  Seung Pil KO ,  Jung Hyuk LEE ,  Shinhee HAN ,  Gwan-Hyeob KOH ,  Yoonjong SONG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

公开(公告)号：US20170250339A1

公开(公告)日：2017-08-31

申请号：US15332042

申请日：2016-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Rie SIM ,  Dae-Hwan KANG ,  Gwan-Hyeob KOH

IPC: H01L45/00 ,  H01L43/10 ,  H01L43/08

CPC classification number: H01L45/1233 ,  H01L27/2427 ,  H01L27/2481 ,  H01L43/08 ,  H01L43/10 ,  H01L45/04 ,  H01L45/06 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1675

Abstract: A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.

公开(公告)号：US20190326355A1

公开(公告)日：2019-10-24

申请号：US16161370

申请日：2018-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsu SON ,  Seung Pil KO ,  Jung Hyuk LEE ,  Shinhee HAN ,  Gwan-Hyeob KOH ,  Yoonjong SONG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.